Table of Contents

• A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL DescriptionSatoshi Ohtake, Michiko Inoue, Hideo Fujiwara. 5-12 [doi]
• Automatic Test Pattern Generation for Improving the Fault Coverage of MicroprocessorsJunichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki. 13-19 [doi]
• On Compact Test Sets for Multiple Stuck-at Faults for Large CircuitsSeiji Kajihara, Atsushi Murakami, Tomohisa Kaneko. 20-24 [doi]
• Identification of Feedback Bridging Faults with OscillationMasaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada. 25 [doi]
• Defining SRAM Resistive Defects and Their Simulation StimuliA. J. van de Goor, J. E. Simonse. 33-40 [doi]
• Vector-Based Functional Fault Models for Delay FaultsIrith Pomeranz, Sudhakar M. Reddy. 41-46 [doi]
• Easily Path Delay Fault Testable Non-Restoring Cellular Array DividersG. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos. 47-52 [doi]
• March Tests for Word-Oriented Two-Port MemoriesSaid Hamdioui, A. J. van de Goor. 53 [doi]
• An Evaluation of Test Generation Algorithms for combinational CircuitsShiyi Xu, Tukwasibwe Justaf Frank. 63-69 [doi]
• Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational CircuitsZhide Zeng, Jihua Chen, Hefeng Cao. 70-74 [doi]
• Pattern Sensitivity: A Property to Guide Test Generation for Combinational CircuitsIrith Pomeranz, Sudhakar M. Reddy. 75-80 [doi]
• An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to Facilitate Test Generation and Fault SimulationJing-Jou Tang. 81 [doi]
• Circuit Partitioning for Low Power BIST Design with Minimized Peak Power ConsumptionPatrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. 89-94 [doi]
• A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STDWenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi. 95-100 [doi]
• Test Scheduling with Loop Folding and Its Application to Test Configurations with AccumulatorsAlbrecht P. Stroele, Frank Mayer. 101-106 [doi]
• A Polynomial-Time Algorithm for Power Constrained Testing of Core Based SystemsC. P. Ravikumar, Ashutosh Verma, Gaurav Chandra. 107-112 [doi]
• Accelerating Test Data ProcessinSerge N. Demidenko, Kenneth V. Lever. 113 [doi]
• Procedure to Overcome the Byzantine General s Problem for Bridging Faults in CMOS CircuitsArabi Keshk, Kozo Kinoshita, Yukiya Miura. 121-126 [doi]
• A Novel Fault-Detection Technique for The Parallel Multipliers and DividersChanyutt Arjhan, Raghvendra G. Deshmukh. 127-132 [doi]
• A Fault Partitioning Method in Parallel Test Generation for Large Scale VLSI CircuitsZhide Zeng, Jihua Chen, Pengxia Liu. 133 [doi]
• Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential CircuitsYoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita. 141-146 [doi]
• On an Effective Selection of IDDQ Measurement Vectors for Sequential CircuitsHideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara. 147-152 [doi]
• Scan Chain Diagnosis Using IDDQ Current MeasurementJunichi Hirase, Naoki Shindou, Kouji Akahori. 153-157 [doi]
• IDDQ Current Dependency on Test Vectors and Bridging ResistanceArabi Keshk, Kozo Kinoshita, Yukiya Miura. 158-163 [doi]
• A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational CircuitsTsuyoshi Shinogi, Terumine Hayashi. 164 [doi]
• An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential CircuitsHsing-Chung Liang, Chung-Len Lee. 173-178 [doi]
• Genetic Algorithm Based Test Generation for Sequential CircuitsLi Shen. 179-184 [doi]
• Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test GenerationMario H. Konijnenburg, Hans van der Linden, A. J. van de Goor. 185-191 [doi]
• Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion ModelToshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara. 192 [doi]
• Activation Function Manipulation for Fault Tolerant Feedforward Neural NetworksYasuyuki Taniguchi, Naotake Kamiura, Yutaka Hata, Nobuyuki Matsui. 203-208 [doi]
• Fault-Tolerant Analysis of Feedback Neural Networks with Threshold NeuronsTao Zhang, Dongcheng Hu, Shiyuan Yang. 209-213 [doi]
• Fault-Tolerant Strategies and Their Design Methods for Application SoftwareJianhua Gao, Shihuang Shao. 214-217 [doi]
• Test by Distributed MonitoringChenglian Peng, Baifeng Wu, Xiaoguang Sun. 218 [doi]
• Optimized Statistical Analog Fault SimulationAbdelhakim Khouas, Mohamed Dessouky, Anne Derieux. 227-232 [doi]
• Analog Metrology and Stimulus Selection in a Noisy EnvironmentChauchin Su, Yue-Tsang Chen, Chung-Len Lee. 233-238 [doi]
• Efficient Test Set Design for Analog and Mixed-Signal Circuits and SystemsSam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg, Mani Soma. 239 [doi]
• Railway Signaling Safety-critical Software Testing Based on Dynamic Decision TableFangmei Wu, Meng Li. 247-250 [doi]
• A Novel Testing Approach for Safety-Critical SoftwareZhongwei Xu, Fangmei Wu. 251-255 [doi]
• How to Design an Environment Simulator for Safety Critical Software TestingHaiying Tu, Fangmei Wu. 256 [doi]
• New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault EfficiencyDebesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara. 263-268 [doi]
• Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware ResetTeruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi, Koji Yamazaki. 269-274 [doi]
• An Embedded Core DFT Scheme to Obtain Highly Compressed Test SetsAbhijit Jas, Kartik Mohanram, Nur A. Touba. 275 [doi]
• Scenario Based Integration Testing for Object-Oriented Software DevelopmentYoungchul Kim, C. Robert Carlson. 283-288 [doi]
• An Approach to Testing the Nonexistence of Initial State in Z SpecificationsHuaikou Miao, Xiaolei Gao, Ling Liu. 289-294 [doi]
• Generating Test Cases for Real-Time Software by Time Petri Nets ModelIan Ho, Jin-Cherng Lin. 295-300 [doi]
• Defect Level Prediction Using Multi-Model Fault CoverageShyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu. 301 [doi]
• A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic StructureTomoya Takasaki, Hideo Fujiwara, Tomoo Inoue. 309-314 [doi]
• An Input Control Technique for Power Reduction in Scan Circuits During Test ApplicationTsung-Chu Huang, Kuen-Jong Lee. 315-320 [doi]
• A Simplified Method for Testing the IBM Pipeline Partial-Scan MicroprocessorXinghao Chen, Thomas J. Snethen, Joe Swenton, Ron Walther. 321-326 [doi]
• A New Algorithm for Retiming-Based Partial ScanZulan Huang, Yizheng Ye, Zhigang Mao. 327 [doi]
• Intelligent EB Test System for Automatic VLSI Fault TracingKatsuyoshi Miura, Koji Nakamae, Hiromu Fujioka. 335-341 [doi]
• Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault SimulatorsHiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Nobuhiro Yanagida. 341-346 [doi]
• Practical Application of Automated Fault Diagnosis for Stuck-at, Bridging, and Measurement Condition Dependent Faults in Fully Scanned Sequential CircuitsReisuke Shimoda, Takaki Yoshida, Masafumi Watari, Yasuhiro Toyota, Kiyokazu Nishi, Akira Motohara. 347 [doi]
• Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAsYinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi. 357-362 [doi]
• Minimizing the Number of Test Configurations for Different FPGA FamiliesMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. 363-368 [doi]
• Testing the Logic Cells and Interconnect Resources for FPGAsAbderrahim Doumar, Hideo Ito. 369-374 [doi]
• IDDQ Testing of Input/Output Resources of SRAM-Based FPGAsLan Zhao, D. M. H. Walker, Fabrizio Lombardi. 375 [doi]
• Failure Analysis Case Studies Using the IR-OBIRCH (Infrared Optical Beam Induced Resistance CHange) MethodKiyoshi Nikawa, Shoji Inoue, Kazuyuki Morimoto, Shinya Sone. 383-388 [doi]
• Investigation of Ga Contamination Due to Analysis by Dual Beam FIBTakahide Sakata, Hideyuki Takahashi, Tetsu Sekine, Toshiya Ogiwara. 389-393 [doi]
• Failure Analysis Case Studies Using the IR-OBIRCH (Infrared Optical Beam Induced Resistance CHange) MethodKiyoshi Nikawa, Shoji Inoue, Kazuyuki Morimoto, Shinya Sone. 394 [doi]