Abstract is missing.
- CA Based Built-In Self-Test Structure for SoCSukanta Das, Biplab K. Sikdar. 3-8 [doi]
- A Random Jitter RMS Estimation Technique for BIST ApplicationsJae-Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham. 9-14 [doi]
- A Novel Seed Selection Algorithm for Test Time Reduction in BISTRupsa Chakraborty, Dipanwita Roy Chowdhury. 15-20 [doi]
- Logic BIST Architecture for System-Level Test and DiagnosisJun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, Feifei Zhao, Laung-Terng Wang. 21-26 [doi]
- Fault Diagnosis under Transparent-ScanIrith Pomeranz, Sudhakar M. Reddy. 29-34 [doi]
- Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG PatternsYu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen. 35-40 [doi]
- On Improving Diagnostic Test Generation for Scan Chain FailuresXun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang. 41-46 [doi]
- On Scan Chain Diagnosis for Intermittent FaultsDan Adolfsson, Joanna Siew, Erik Jan Marinissen, Erik Larsson. 47-54 [doi]
- Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction TechniqueJin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang. 57-62 [doi]
- Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial CoefficientsSuraj Sindia, Virendra Singh, Vishwani D. Agrawal. 63-68 [doi]
- Low Cost Dynamic Test Methodology for High Precision ΣD ADCsS. Kook, Hyun Choi, Vishwanath Natarajan, Abhijit Chatterjee, Alfred V. Gomes, Shalabh Goyal, Le Jin. 69-74 [doi]
- Very-Low-Voltage Testing of Amorphous Silicon TFT CircuitsShiue-Tsung Shen, Wei-Hsiao Liu, En-Hua Ma, James Chien-Mo Li, I-Chun Cheng. 75-80 [doi]
- Scan Compression Implementation in Industrial Design - Case StudyDragon Hsu, Ron Press. 83-84 [doi]
- Calibration as a Functional Test: An ADC Case StudyHsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting Cheng. 85-86 [doi]
- Customized Algorithms for High Performance Memory Test in Advanced Technology NodeShomo Chen, Ning Huang, Ting-Pu Tai, Actel Niu. 87-89 [doi]
- A Practical DFT Approach for Complex Low Power DesignsAugusli Kifli, Y.-W. Chen, Yu-Wen Tsai, Kun-Cheng Wu. 90-91 [doi]
- DFT Challenges in Next Generation Multi-media IPMukund Mittal, Subrangshu Das, S. Vishwanath. 92-93 [doi]
- Yield Ramp up by Scan Chain DiagnosisFeng-Ming Kuo, Yuan-Shih Chen. 94-95 [doi]
- CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan TestingK. Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, M. Aso, Hiroshi Furukawa. 99-104 [doi]
- New Scheme of Reducing Shift and Capture Power Using the X-Filling MethodologyTsung-Tang Chen, Wei-Lin Li, Po-Han Wu, Jiann-Chyi Rau. 105-110 [doi]
- Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan TestingLung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chi-Wei Yu. 111-116 [doi]
- Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 DecoderMing Gao, Kwang-Ting Cheng. 119-124 [doi]
- A FPGA-Based Reconfigurable Software Architecture for Highly Dependable SystemsStefano Di Carlo, Paolo Prinetto, Alberto Scionti. 125-130 [doi]
- Using Non-trivial Logic Implications for Trace Buffer-Based Silicon DebugSandesh Prabhakar, Michael Hsiao. 131-136 [doi]
- A Post-Silicon Debug Support Using High-Level Design DescriptionYeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita. 137-142 [doi]
- A Low Overhead On-Chip Path Delay Measurement CircuitSongwei Pei, Huawei Li, Xiaowei Li. 145-150 [doi]
- An Adaptive Test for Parametric Faults Based on Statistical Timing InformationMichihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu. 151-156 [doi]
- A Delay Measurement Technique Using Signature RegistersKentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito. 157-162 [doi]
- Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self TestChen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li. 163-168 [doi]
- A Practical Approach to Threshold Test Generation for Error Tolerant CircuitsHideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue. 171-176 [doi]
- Speeding up SAT-Based ATPG Using Dynamic Clause ActivationStephan Eggersglüß, Daniel Tille, Rolf Drechsler. 177-182 [doi]
- N-distinguishing Tests for Enhanced Defect DiagnosisGang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz. 183-186 [doi]
- Dynamic Compaction in SAT-Based ATPGAlejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker. 187-190 [doi]
- SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area ImprovementMohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta. 193-199 [doi]
- Transaction Level Modeling and Design Space Exploration for SOC Test ArchitecturesChin-Yao Chang, Chih-Yuan Hsiao, Kuen-Jong Lee, Alan P. Su. 200-205 [doi]
- Efficient Software-Based Self-Test Methods for Embedded Digital Signal ProcessorsJun-Jie Zhu, Wen-Ching Lin, Jheng-Hao Ye, Ming-Der Shieh. 206-211 [doi]
- Is Low Power Testing Necessary? What does the Test Industry Truly Need?Anis Uzzaman. 215-216 [doi]
- A Scalable Scan Architecture for Godson-3 Multicore MicroprocessorZichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu. 219-224 [doi]
- Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application TimeMichael S. Hsiao, Mainak Banga. 225-230 [doi]
- Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output ConstraintKatherine Shu-Min Li, Yu-Chen Hung, Jr-Yang Huang. 231-236 [doi]
- Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault TestingK. G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh. 237-240 [doi]
- BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient SearchVishwanath Natarajan, Shyam Kumar Devarakond, Shreyas Sen, Abhijit Chatterjee. 243-248 [doi]
- Self-Calibrating Embedded RF Down-Conversion MixersAbhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee. 249-254 [doi]
- A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response AnalysisManuel J. Barragan Asian, Rafaella Fiorelli, Diego Vázquez, Adoración Rueda, José Luis Huertas. 255-260 [doi]
- Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATENicolas Pous, Florence Azaïs, Laurent Latorre, Pascal Nouet, Jochen Rivoir. 261-266 [doi]
- IEEE 1500 Compatible Interconnect Test with Maximal Test ConcurrencyKatherine Shu-Min Li, Yi-Yu Liao, Yuo-Wen Liu, Jr-Yang Huang. 269-274 [doi]
- Multiple-Core under Test Architecture for HOY Wireless Testing PlatformSung-Yu Chen, Ying-Yen Chen, Chun-Yu Yang, Jing-Jia Liou. 275-280 [doi]
- Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron TechnologiesChunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan. 281-286 [doi]
- Test Integration for SOC Supporting Very Low-Cost TestersChun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu. 287-292 [doi]
- Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman. 295-300 [doi]
- New Class of Tests for Open Faults with Considering Adjacent LinesHiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume. 301-306 [doi]
- Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power ConsumptionSubhadip Kundu, S. Krishna Kumar, Santanu Chattopadhyay. 307-312 [doi]
- Deterministic Algorithms for ATPG under Leakage ConstraintsGorschwin Fey. 313-316 [doi]
- Extended Selective Encoding of Scan Slices for Reducing Test Data and Test PowerJun Liu, Yinhe Han, Xiaowei Li. 319-324 [doi]
- A Multi-dimensional Pattern Run-Length Method for Test Data CompressionLung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chen-Lun Lee. 325-330 [doi]
- Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect CoverageHongxia Fang, Krishnendu Chakrabarty, Rubin A. Parekhji. 331-336 [doi]
- Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?Said Hamdioui. 339 [doi]
- A Non-Intrusive and Accurate Inspection Method for Segment Delay VariabilitiesYing-Yen Chen, Jing-Jia Liou. 343-348 [doi]
- Bridging Fault Diagnosis to Identify the Layer of Systematic DefectsPo-Juei Chen, James Chien-Mo Li, Hsing Jasmine Chao. 349-354 [doi]
- Delay Fault Diagnosis in Sequential CircuitsYoussef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer. 355-360 [doi]
- A Partially-Exhaustive Gate Transition Fault ModelBrion L. Keller, Dale Meehl, Anis Uzzaman, Richard Billings. 361-364 [doi]
- An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits TestingChen-Yuan Yang, Xuan-Lun Huang, Jiun-Lang Huang. 367-372 [doi]
- LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal CircuitsJoonsung Park, Jaeyong Chung, Jacob A. Abraham. 373-378 [doi]
- A Jitter Characterizing BIST with Pulse-Amplifying TechniqueAn-Sheng Chao, Soon-Jyh Chang. 379-384 [doi]
- A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting MethodShao-Feng Hung, Hao-Chiao Hong, Sheng-Chuan Liang. 385-388 [doi]
- New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance FaultsA. J. van de Goor, Said Hamdioui, Georgi Nedeltchev Gaydadjiev, Zaid Al-Ars. 391-396 [doi]
- Testability Exploration of 3-D RAMs and CAMsYu-Jen Huang, Jin-Fu Li. 397-402 [doi]
- Fault Diagnosis Using Test Primitives in Random Access MemoriesZaid Al-Ars, Said Hamdioui. 403-408 [doi]
- Test Generation for Designs with On-Chip Clock GeneratorsXijiang Lin, Mark Kassab. 411-417 [doi]
- On the Generation of Functional Test Programs for the Cache Replacement LogicWilson J. Perez, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda. 418-423 [doi]
- Compact Test Generation for Small-Delay Defects Using Testable-Path InformationDong Xiang, Boxue Yin, Krishnendu Chakrabarty. 424-429 [doi]
- At-Speed Scan Test Method for the Timing Optimization and CalibrationKun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng. 430-433 [doi]
- M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced DelaySong Jin, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, Guihai Yan. 437-442 [doi]
- Analysis of Resistive Bridging Defects in a SynchronizerHyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu. 443-449 [doi]
- On-Chip TSV Testing for 3D IC before Bonding Using Sense AmplificationPo-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai. 450-455 [doi]
- Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution NetworksYubin Zhang, Lin Huang, Feng Yuan, Qiang Xu. 456-461 [doi]