Table of Contents

• On Detecting Transition Faults in the Presence of Clock Delay FaultsYoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja. 1-6 [doi]
• Testing of Clock-Domain Crossing Faults in Multi-core System-on-ChipNaghmeh Karimi, Zhiqiu Kong, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil. 7-14 [doi]
• On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing TestHyunjin Kim, Jacob A. Abraham. 15-20 [doi]
• Time Domain Characterization and Test of High Speed Signals Using Incoherent Sub-samplingDebesh Bhatta, Joshua W. Wells, Abhijit Chatterjee. 21-26 [doi]
• Temperature Dependent Test Scheduling for Multi-core System-on-ChipChunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan. 27-32 [doi]
• Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage IslandsXrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji. 33-39 [doi]
• Selective Test Response Collection for Low-Power Scan Testing with Well-Compressed Test DataDong Xiang, Zhen Chen. 40-45 [doi]
• Low Power Test-Compression for High Test-Quality and Low Test-Data VolumeVasileios Tenentes, Xrysovalantis Kavousianos. 46-53 [doi]
• Multi-cycle Test with Partial Observation on Scan-Based BIST StructureYasuo Sato, Hisato Yamaguchi, Makoto Matsuzono, Seiji Kajihara. 54-59 [doi]
• SSTKR: Secure and Testable Scan Design through Test Key RandomizationMohammed Abdul Razzaq, Virendra Singh, Adit D. Singh. 60-65 [doi]
• An Innovative Methodology for Scan Chain Insertion and Analysis at RTLLilia Zaourar, Yann Kieffer, Chouki Aktouf. 66-71 [doi]
• Adaptation of Standard RT Level BIST Architectures for System Level Communication TestingNastaran Nemati, Zainalabedin Navabi. 72-77 [doi]
• Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift TestingOzgur Sinanoglu. 78-83 [doi]
• Low Power Decompressor and PRPG with Constant Value BroadcastMichal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer. 84-89 [doi]
• Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-FillingKohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel. 90-95 [doi]
• Virtual Circuit Model for Low Power Scan Testing in Linear Decompressor-Based Compression EnvironmentZhen Chen, Jia Li, Dong Xiang, Yu Huang. 96-101 [doi]
• Test Pattern Selection for Defect-Aware TestYoshinobu Higami, Hiroshi Furutani, Takao Sakai, Shuichi Kameyama, Hiroshi Takahashi. 102-107 [doi]
• Efficient SAT-Based Search for Longest Sensitisable PathsMatthias Sauer, Jie Jiang, Alejandro Czutro, Ilia Polian, Bernd Becker. 108-113 [doi]
• Mapping Transaction Level Faults to Stuck-At Faults in Communication HardwareFatemeh Javaheri, Majid Namaki-Shoushtari, Parastoo Kamranfar, Zainalabedin Navabi. 114-119 [doi]
• On Generation of 1-Detect TDF Pattern Set with Significantly Increased SDD CoverageFang Bao, Ke Peng, Krishnendu Chakrabarty, Mohammad Tehranipoor. 120-125 [doi]
• Yield-per-Area Optimization for 6T-SRAMs Using an Integrated Approach to Exploit Spares and ECC to Efficiently Combat High Defect and Soft-Error RatesJae Chul Cha, Sandeep K. Gupta. 126-135 [doi]
• A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital CircuitsD. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich. 136-141 [doi]
• A New Architecture to Cross-Fertilize On-Line and Manufacturing TestingPaolo Bernardi, Matteo Sonza Reorda. 142-147 [doi]
• Online Test Macro Scheduling and Assignment in MPSoC DesignB. Khodabandeloo, Seyyed Alireza Hoseini, S. Taheri, M. H. Haghbayan, M. R. Babaei, Zainalabedin Navabi. 148-153 [doi]
• Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process VariationsJayaram Natarajan, Joshua W. Wells, Abhijit Chatterjee, Adit D. Singh. 154-160 [doi]
• An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip MultiprocessorsRance Rodrigues, Sandip Kundu. 161-166 [doi]
• An Efficient 2-Phase Strategy to Achieve High Branch CoverageSarvesh Prabhu, Michael S. Hsiao, Saparya Krishnamoorthy, Loganathan Lingappan, Vijay Gangaram, Jim Grundy. 167-174 [doi]
• Soft Error Recovery Technique for Multiprocessor SOPCUros Legat, Anton Biasizzo, Franc Novak. 175-180 [doi]
• Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoCYuanqing Cheng, Lei Zhang 0008, Yinhe Han, Jun Liu, Xiaowei Li 0001. 181-186 [doi]
• Identification of Defective TSVs in Pre-Bond Testing of 3D ICsBrandon Noia, Krishnendu Chakrabarty. 187-194 [doi]
• A Unified Interconnects Testing Scheme for 3D Integrated CircuitsChih-Yun Pai, Ruei-Ting Gu, Bo-Chuan Cheng, Liang-Bi Chen, Katherine Shu-Min Li. 195-200 [doi]
• Cost-Effective TSV Grouping for Yield Improvement of 3D-ICsYi Zhao, S. Saqib Khursheed, Bashir M. Al-Hashimi. 201-206 [doi]
• Improved Fault Diagnosis for Reversible CircuitsHongyan Zhang, Robert Wille, Rolf Drechsler. 207-212 [doi]
• Embedded Test for Highly Accurate Defect LocalizationAbdullah Mumtaz, Michael E. Imhof, Stefan Holst, Hans-Joachim Wunderlich. 213-218 [doi]
• On Using Design Partitioning to Reduce Diagnosis Memory FootprintXiaoxin Fan, Huaxing Tang, Sudhakar M. Reddy, Wu-Tung Cheng, Brady Benware. 219-225 [doi]
• Exploring Impact of Faults on Branch Predictors' Power for Diagnosis of Faulty ModuleGunjan Bhattacharya, Ilora Maity, Biplab K. Sikdar, Baisakhi Das. 226-231 [doi]
• Post-Silicon Timing Validation Method Using Path Delay MeasurementsEun-jung Jang, Jaeyong Chung, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham. 232-237 [doi]
• Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation TracesAnvesh Komuravelli, Srobona Mitra, Ansuman Banerjee, Pallab Dasgupta. 238-243 [doi]
• Design of a Test Processor for Asynchronous Chip TestSteffen Zeidler, Christoph Wolf, Milos Krstic, Frank Vater, Rolf Kraemer. 244-250 [doi]
• On Generating Vectors for Accurate Post-Silicon Delay CharacterizationPrasanjeet Das, Sandeep K. Gupta. 251-260 [doi]
• Predicting Scan Compression IP Configurations for Better QoRJyotirmoy Saikia, Pramod Notiyath, Santosh Kulkarni, Ashok Anbalan, Rajesh Uppuluri, Tammy Fernandes, Parthajit Bhattacharya, Rohit Kapur. 261-266 [doi]
• Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-GatingElham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki. 267-272 [doi]
• Test Compression Based on Lossy Image EncodingHideyuki Ichihara, Yuka Iwamoto, Yuki Yoshikawa, Tomoo Inoue. 273-278 [doi]
• Multiscan-based Test Data Compression Using UBI Dictionary and BitmaskYang Yu, Gang Xi, Liyan Qiao. 279-284 [doi]
• Diagnostic Test of Robust CircuitsAlejandro Cook, Sybille Hellebrand, Thomas Indlekofer, Hans-Joachim Wunderlich. 285-290 [doi]
• An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay DefectsPo-Juei Chen, Wei-Li Hsu, James Chien-Mo Li, Nan-Hsin Tseng, Kuo-Yin Chen, Wei-pin Changchien, Charles C. C. Liu. 291-296 [doi]
• Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic DefectsZhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya. 297-302 [doi]
• Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process VariationsXi Qian, Adit D. Singh, Abhijit Chatterjee. 303-310 [doi]
• A Process Monitor Based Speed Binning and Die Matching AlgorithmSreejit Chakravarty. 311-316 [doi]
• Optimized Test Error Detection by Probabilistic Retest Recommendation ModelsMatthias Kirmse, Uwe Petersohn, Elief Paffrath. 317-322 [doi]
• Adaptive Test Framework for Achieving Target Test Quality at Minimal CostBaris Arslan, Alex Orailoglu. 323-328 [doi]
• A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video ApplicationsYuntan Fang, Huawei Li, Xiaowei Li 0001. 329-334 [doi]
• Efficient Use of Unused Spare Columns to Improve Memory Error Correcting RateUmair Ishaq, Jihun Jung, Jaehoon Song, Sungju Park. 335-340 [doi]
• New Fault Detection Algorithm for Multi-level Cell Flash MemroiesJaewon Cha, Ilwoong Kim, Sungho Kang. 341-346 [doi]
• A New Test Paradigm for Semiconductor Memories in the Nano-EraSaid Hamdioui, Venkataraman Krishnaswami, Ijeoma Sandra Irobi, Zaid Al-Ars. 347-352 [doi]
• On Defect Oriented Testing for Hybrid CMOS/Memristor MemoryNor Zaidi Haron, Said Hamdioui, Nor Zaidi Haron. 353-358 [doi]
• Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAsManuel J. Barragan Asian, Rafaella Fiorelli, Gildas Leger, Adoración Rueda, José L. Huertas. 359-364 [doi]
• On Replacing an RF Test with an Alternative Measurement: Theory and a Case StudyAlexios Spyronasios, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir. 365-370 [doi]
• Test and Diagnosis of Analog Circuits Using Moment Generating FunctionsSuraj Sindia, Vishwani D. Agrawal, Virendra Singh. 371-376 [doi]
• Mixed-Signal Fault Equivalence: Search and EvaluationNuno Guerreiro, Marcelino Santos. 377-382 [doi]
• Efficient BDD-based Fault Simulation in Presence of Unknown ValuesMichael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich. 383-388 [doi]
• Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process VariationShida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Krishnendu Chakrabarty. 389-394 [doi]
• Automation of 3D-DfT InsertionSergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario H. Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel. 395-400 [doi]
• MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data CachesStefano Di Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Paolo Prinetto. 401-406 [doi]
• Testing for Parasitic Memory Effect in SRAMsSandra Irobi, Zaid Al-Ars, Said Hamdioui, Claude Thibeault. 407-412 [doi]
• Transient Noise Failures in SRAM Cells: Dynamic Noise Margin MetricElena I. Vatajelu, Alvaro Gómez-Pau, Michel Renovell, Joan Figueras. 413-418 [doi]
• Fault Diagnosis in Memory BIST Environment with Non-march TestsGrzegorz Mrugalski, Artur Pogiel, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Pawel Urbanek. 419-424 [doi]
• Characterizing Pattern Dependent Delay Effects in DDR Memory InterfacesAtul Gupta, Ajay Kumar, Manas Chhabra. 425-431 [doi]
• Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C)Anshuman Chandra, Jyotirmoy Saikia, Rohit Kapur. 432-437 [doi]
• Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAsKeheng Huang, Yu Hu, Xiaowei Li 0001, Gengxin Hua, Hongjin Liu, Bo Liu. 438-443 [doi]
• A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA InterconnectsHaider A. F. Almurib, T. Nandha Kumar, Fabrizio Lombardi. 444-450 [doi]
• Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer BaseChun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu. 451-456 [doi]
• Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCsV. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra. 457-458 [doi]
• Failure Analysis and Test Solutions for Low-Power SRAMsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine. 459-460 [doi]
• A Robust Solution for Embedded Memory Test and RepairK. Darbinyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian. 461-462 [doi]
• Nand Flash Memory - Product Trends, Technology Overview, and Technical ChallengesManuel A. d'Abreu. 463 [doi]
• High Level Verification and Its Use at Pos-Silicon Debugging and PatchingMasahiro Fujita. 464-469 [doi]
• 3D Specific Systems: Design and CADPaul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson, Samson Melamed. 470-473 [doi]
• Testing and Design-for-Testability Techniques for 3D Integrated CircuitsBrandon Noia, Krishnendu Chakrabarty. 474-479 [doi]
• Yield Improvement and Test Cost Optimization for 3D Stacked ICsSaid Hamdioui, Mottaqiallah Taouil. 480-485 [doi]
• Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test CostAshish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst, Kaushik Roy. 486-491 [doi]
• Dependable VLSI Program in Japan: Program Overview and the Current Status of Dependable VLSI Platform ProjectHidetoshi Onodera. 492-495 [doi]
• Reliability: A Cross-Disciplinary and Cross-Layer ApproachNorbert Wehn. 496-497 [doi]
• Underdesigned and Opportunistic ComputingPuneet Gupta, Rajesh K. Gupta. 498-499 [doi]
• Power Aware Shift and Capture ATPG Methodology for Low Power DesignsShray Khullar, Swapnil Bahl. 500-505 [doi]
• Power-Aware Test Pattern Generation for At-Speed LOS TestingAlberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, X. Wen. 506-510 [doi]
• Power Aware Embedded TestXijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer. 511-516 [doi]
• Testability of Cryptographic Hardware and Detection of Hardware TrojansDebdeep Mukhopadhyay, Rajat Subhra Chakraborty. 517-524 [doi]
• Test Scheduling in an IEEE P1687 Environment with Resource and Power ConstraintsFarrokh Ghani Zadegan, Urban Ingelsson, Golnaz Asani, Gunnar Carlsson, Erik Larsson. 525-531 [doi]
• Automatic SoC Level Test Path Synthesis Based on Partial Functional ModelsAnton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze. 532-538 [doi]
• A Boundary Scan Circuit with Time-to-Digital Converter for Delay TestingHiroyuki Yotsuyanagi, Hiroyuki Makimoto, Masaki Hashizume. 539-544 [doi]
• Burst-Mode Transmission and Data Recovery for Multi-GHz Optical Packet Switching Network TestingCarl Gray, David C. Keezer, Howard Wang, Keren Bergman. 545-551 [doi]