Table of Contents

• An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock WaveformsHiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Masahiro Takakura. 1 [doi]
• LBIST/ATPG Technologies for On-Demand Digital Logic Testing in Automotive CircuitsDale Meehl, Bassilios Petrakis, Ping Zhang. 2 [doi]
• Portable/Desktop Testing Solution for Engineering with CloudNobutaka Takahashi, Toshiaki Watanabe, Takehisa Suzuki, Manabu Kimura. 3 [doi]
• Characteristics Variability Evaluation of Actual LSI Transistors with NanoprobingMunetoshi Fukui, Yasuhiko Nara, Junichi Fuse. 4 [doi]
• F-matrix (ABCD-matrix) Circuit Simulation Built in IC Test ProgramHideo Okawara. 5 [doi]
• Addressing Test Challenges in Advanced Technology NodesYervant Zorian. 6 [doi]
• Diagnosis of Cell Internal Defects with Multi-cycle Test PatternsXiaoxin Fan, Manish Sharma, Wu-Tung Cheng, Sudhakar M. Reddy. 7-12 [doi]
• Automated Post-Silicon Debugging of Failing SpeedpathsMehdi Dehbashi, Görschwin Fey. 13-18 [doi]
• SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT InsertionsSatoshi Jo, Takeshi Matsumoto, Masahiro Fujita. 19-24 [doi]
• A New Look Ahead Technique for Customized Testing in Digital Microfluidic BiochipsPranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta, Bhargab B. Bhattacharya. 25-30 [doi]
• TSV Stress-Aware ATPG for 3D Stacked ICsSergej Deutsch, Krishnendu Chakrabarty, Shreepad Panth, Sung Kyu Lim. 31-36 [doi]
• Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated CircuitsSpencer K. Millican, Kewal K. Saluja. 37-42 [doi]
• Programmable Leakage Test and Binning for TSVsYu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng. 43-48 [doi]
• Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarkingIlia Polian. 49 [doi]
• Counting Gates, Moving Qubits: Evaluating the Execution Cost of Quantum CircuitsRodney Van Meter. 50-54 [doi]
• Programming a Topological Quantum ComputerSimon Devitt, Kae Nemoto. 55-60 [doi]
• An Optimization Problem for Topological Quantum ComputationShigeru Yamashita. 61-66 [doi]
• Session Summary II: Dependable VLSI for Product ReliabilityXinli Gu. 67 [doi]
• Soft Error Issues with Scaling TechnologiesSanghyeon Baeg, Jongsun Bae, Soonyoung Lee, Chul Seung Lim, Sang Hoon Jeon, Hyeonwoo Nam. 68 [doi]
• In-Field Testing of NAND Flash Storage: Why and How?Yu Hu, Xinli Gu, Xiaowei Li 0001. 69 [doi]
• A Few Design Techniques for the "Dependability" of a SOCJun Qian. 70 [doi]
• Accessing Embedded DfT Instruments with IEEE P1687Erik Larsson, Farrokh Ghani Zadegan. 71-76 [doi]
• Multi-level EDT to Reduce Scan Channels in SoC DesignsGuoliang Li, Jun Qian, Peter Li, Greg Zuo. 77-82 [doi]
• On Utilizing Test Cube Properties to Reduce Test Data Volume FurtherXijiang Lin, Janusz Rajski. 83-88 [doi]
• Note on Layout-Aware Weighted Probabilistic Bridge Fault CoverageMasayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki. 89-94 [doi]
• Tailoring Tests for Functional Binning of Integrated CircuitsSuraj Sindia, Vishwani D. Agrawal. 95-100 [doi]
• A Thermal-Driven Test Application Scheme for 3-Dimensional ICsDong Xiang, Kele Shen, Yangdong Deng. 101-106 [doi]
• A Transition Isolation Scan Cell Design for Low Shift and Capture PowerYi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen. 107-112 [doi]
• A Probabilistic and Constraint Based Approach for Low Power Test GenerationHossein Sabaghian Bidgoli, Majid Namaki-Shoushtari, Zainalabedin Navabi. 113-118 [doi]
• Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay DetectionYoshihiro Ohkawa, Yukiya Miura. 119-124 [doi]
• Impact of Resistive-Bridge Defects in TAS-MRAM ArchitecturesJ. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay. 125-130 [doi]
• SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate WriteYuntan Fang, Huawei Li, Xiaowei Li 0001. 131-136 [doi]
• A Generalized Theory for Formal Assertion CoverageSourasis Das, Ansuman Banerjee, Pallab Dasgupta. 137-142 [doi]
• Error Model Free Automatic Design Error Correction of Complex Processors Using Formal MethodsAmir Masoud Gharehbaghi, Masahiro Fujita. 143-148 [doi]
• Hardware-Accelerated Workload Characterization for Power Modeling and Fault InjectionArmin Krieg, Johannes Grinschgl, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid. 149-154 [doi]
• Scan Test Power Simulation on GPGPUsStefan Holst, Eric Schneider, Hans-Joachim Wunderlich. 155-160 [doi]
• Power Supply Noise Sensor Based on Timing Uncertainty MeasurementsMiroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, P. Debaud, S. Guilhot. 161-166 [doi]
• Peak Power Estimation: A Case Study on CPU CoresPaolo Bernardi, M. De Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Patrick Girard, Miroslav Valka. 167-172 [doi]
• Low Power BIST for Scan-Shift and Capture PowerYasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara. 173-178 [doi]
• Two-Tone Signal Generation for Communication Application ADC TestingKeisuke Kato, Fumitaka Abe, Kazuyuki Wakabayashi, Chuan Gao, Takafumi Yamada, Haruo Kobayashi, Osamu Kobayashi, Kiichi Niitsu. 179-184 [doi]
• A New Procedure for Measuring High-Accuracy Probability Density FunctionsTakahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira. 185-190 [doi]
• Design of a High Bandwidth Interposer for Performance Evaluation of ATE Test Fixtures at the DUT SocketJose Moreira. 191-195 [doi]
• Spectral Estimation Based Acquisition of Incoherently Under-sampled Periodic Signals: Application to Bandwidth InterleavingDebesh Bhatta, Nicholas Tzou, Hyun Woo Choi, Abhijit Chatterjee. 196-201 [doi]
• Adaptive Board-Level Functional Fault Diagnosis Using Decision TreesFangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. 202-207 [doi]
• Board-Level Functional Fault Diagnosis Using Learning Based on Incremental Support-Vector MachinesFangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. 208-213 [doi]
• Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICsAlejandro Cook, Dominik Ull, Melanie Elm, Hans-Joachim Wunderlich, Helmut Randoll, Stefan Dohren. 214-219 [doi]
• Session Summary III: Power-Aware Testing: Present and FutureXiaoqing Wen, Sudhakar M. Reddy. 220 [doi]
• Why and How Controlling Power Consumption during Test: A SurveyAlberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel. 221-226 [doi]
• PowerMAX: Fast Power Analysis during TestWei Zhao, Mohammad Tehranipoor. 227-232 [doi]
• Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network ValidationPrab Varma. 233-238 [doi]
• Power Supply Droop and Its Impacts on Structural At-Speed TestingXijiang Lin. 239-244 [doi]
• Session Summary IV: Post-Silicon Measurements and Tests: Analog Test and High-Speed I/O Test IITakkahiro J. Yamaguchi. 245 [doi]
• A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb IssuesKoji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara, Kazuyoshi Okamoto. 246-251 [doi]
• Impact of All-Digital PLL on SoC TestingToru Nakura, Tetsuya Iizuka, Kunihiro Asada. 252-257 [doi]
• Post-Silicon Jitter MeasurementsKiichi Niitsu, Takahiro J. Yamaguchi, Masahiro Ishida, Haruo Kobayashi. 258-263 [doi]
• An Active Test Fixture Approach for Testing 28 Gbps Applications Using a Lower Data Rate ATE SystemJose Moreira, Bernhard Roth, Callum McCowan. 264-269 [doi]
• Session Summary V: Is Component Interconnection Test Enough for Board or System TestXinli Gu. 270 [doi]
• Embedded Tutorial Summary: Diagnosis for Accelerating Yield and Failure AnalysisWu-Tung Cheng, Feng-Ming Kuo. 271 [doi]
• A Scan-Out Power Reduction Method for Multi-cycle BISTSenling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara. 272-277 [doi]
• A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data VolumeWei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh. 278-283 [doi]
• A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADCY.-H. Chou, J.-L. Huang, X.-L. Huang. 284-289 [doi]
• Robust Timing-Aware Test Generation Using Pseudo-Boolean OptimizationStephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty. 290-295 [doi]
• Functional Pattern Generation for Asynchronous Designs in a Test Processor EnvironmentSteffen Zeidler, Christoph Wolf, Milos Krstic, Rolf Kraemer. 296-301 [doi]
• Reduced-Complexity Transition-Fault Test Generation for Non-scan Circuits through High-Level Mutant InjectionValerio Guarnieri, Franco Fummi, Krishnendu Chakrabarty. 302-307 [doi]
• Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMsShyue-Kung Lu, Tsu-Lin Li, Pony Ning. 308-313 [doi]
• A Hybrid Flow for Memory Failure Bitmap ClassificationJianbo Li, Yu Huang 0005, Wu-Tung Cheng, Chris Schuermyer, Dong Xiang, Eric Faehn, Ruth Farrugia. 314-319 [doi]
• Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test DataJun-Hua Kuo, Ting-Shuo Hsu, Jing-Jia Liou. 320-325 [doi]
• NoC Dynamically Reconfigurable as TAMTakieddine Sbiai, Kazuteru Namba. 326-331 [doi]
• On-Line Error Detection in Digital Microfluidic BiochipsDebasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, Bhargab B. Bhattacharya. 332-337 [doi]
• Automatic Test Program Generation for Out-of-Order Superscalar ProcessorsYing Zhang, Ahmed Rezine, Petru Eles, Zebo Peng. 338-343 [doi]
• Variation-Aware Fault GradingAlexander Czutro, Michael E. Imhof, J. Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich. 344-349 [doi]
• On-Chip Detection of Process Shift and Process Spread for Silicon Debugging and Model-Hardware CorrelationIslam A. K. M. Mahfuzul, Hidetoshi Onodera. 350-354 [doi]
• Efficient Trojan Detection via Calibration of Process VariationsByeongju Cha, Sandeep K. Gupta. 355-361 [doi]