Abstract is missing.
- Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy ConstraintsBing-Yang Lin, Mincent Lee, Cheng-Wen Wu. 1-6 [doi]
- A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICsChi-Chun Yang, Che-Wei Chou, Jin-Fu Li. 7-12 [doi]
- Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICsMasaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi, Shyue-Kung Lu. 13-18 [doi]
- On Achieving Capture Power Safety in At-Speed Scan-Based Logic BISTA. Tomita, X. Wen, Y. Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, L.-T. Wang. 19-24 [doi]
- Thermal Aware Don't Care Filling to Reduce Peak Temperature and Thermal Variance during TestingArpita Dutta, Subhadip Kundu, Santanu Chattopadhyay. 25-30 [doi]
- Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-FillStephan Eggersglussv. 31-36 [doi]
- Worst-Case Critical-Path Delay Analysis Considering Power-Supply NoiseFang Bao, Mohammad Tehranipoor, Harry Chen. 37-42 [doi]
- Test Generation of Path Delay Faults Induced by Defects in Power TSVChi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu, James Chien-Mo Li, Tzong-Lin Wu, Krishnendu Chakrabarty. 43-48 [doi]
- Multicycle-aware At-speed Test MethodologyKun-Han Tsai, Xijiang Lin. 49 [doi]
- Analog Sensor Based Testing of Phase-Locked Loop Dynamic Performance ParametersSen-Wen Hsiao, Xian Wang, Abhijit Chatterjee. 50-55 [doi]
- Built-In Test of Switched-Mode Power Converters: Avoiding DUT Damage Using Alternative Safe MeasurementsXian Wang, Blanchard Kenfack, Estella Silva, Abhijit Chatterjee. 56-61 [doi]
- Design of a Fault-Injectable Fleischer-Laker Switched-Capacitor Biquad for Verifying the Static Linear Behavior Fault ModelLong-Yi Lin, Hao-Chiao Hong. 62-66 [doi]
- Failure Localization of Logic Circuits Using Voltage Contrast Considering State of TransistorsMasafumi Nikaido, Yukihisa Funatsu, Tetsuya Seiyama, Junpei Nonaka, Kazuki Shigeta. 67-72 [doi]
- Handling Missing Syndromes in Board-Level Functional-Fault DiagnosisFangming Ye, Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. 73-78 [doi]
- Diagnosing Resistive Open Faults Using Small Delay Fault SimulationKoji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja. 79-84 [doi]
- A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-TestYuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue. 85-90 [doi]
- Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring OscillatorYingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang. 91-96 [doi]
- A New LFSR Reseeding Scheme via Internal Response FeedbackWei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty. 97-102 [doi]
- Scan Test Data Volume Reduction for SoC Designs in EDT EnvironmentGuoliang Li, Jun Qian, Yuan Zuo, Rui Li, Qinfu Yang. 103-104 [doi]
- Automotive EEPROM Qualification and Cost OptimizationPeter Sarson, Gregor Schatzberger, Robert Seitz. 105-106 [doi]
- Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICsChen-An Chen, Yee-Wen Chen, Chun-Lung Hsu, Ming-Hsueh Wu, Kun-Lun Luo, Bing-Chuan Bai, Liang-Chia Cheng. 107-108 [doi]
- Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM TestingElena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. 109-114 [doi]
- A New March Test for Process-Variation Induced Delay Faults in SRAMsDa Cheng, Hsunwei Hsiung, Bin Liu 0004, Jianing Chen, Jia Zeng, Ramesh Govindan, Sandeep K. Gupta. 115-122 [doi]
- Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAMBing-Chuan Bai, Chun-Lung Hsu, Ming-Hsueh Wu, Chen-An Chen, Yee-Wen Chen, Kun-Lun Luo, Liang-Chia Cheng, James Chien-Mo Li. 123-127 [doi]
- Digital Calibration for 8-Bit Delay Line ADC Using Harmonic Distortion CorrectionHsun-Cheng Lee, Jacob A. Abraham. 128-133 [doi]
- Digital Compensation for Timing Mismatches in Interleaved ADCsRu Yi, Minghui Wu, Koji Asami, Haruo Kobayashi, Ramin Khatami, Atsuhiro Katayama, Isao Shimizu, Kentaroh Katoh. 134-139 [doi]
- An Analysis of Stochastic Self-Calibration of TDC Using Two Ring OscillatorsKentaroh Katoh, Yuta Doi, Satoshi Ito, Haruo Kobayashi, Ensi Li, Nobukazu Takai. 140-146 [doi]
- Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5D ICsRan Wang, Krishnendu Chakrabarty, Bill Eklow. 147-152 [doi]
- Mid-bond Interposer Wire TestLi-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter. 153-158 [doi]
- A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-PackageKatherine Shu-Min Li, Cheng-You Ho, Ruei-Ting Gu, Sying-Jyan Wang, Yingchieh Ho, Jiun-Jie Huang, Bo-Chuan Cheng, An-Ting Liu. 159-164 [doi]
- Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency ScalingSpencer K. Millican, Kewal K. Saluja. 165-170 [doi]
- Search Space Reduction for Low-Power Test GenerationKohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara. 171-176 [doi]
- MIRID: Mixed-Mode IR-Drop Induced Delay SimulatorJ. Jiang, M. Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Ilia Polian. 177-182 [doi]
- A Stochastic Model for NBTI-Induced LSI Degradation in FieldYasuo Sato, Seiji Kajihara. 183-188 [doi]
- Hazard Initialized LOC Tests for TDF Undetectable CMOS Open DefectsChao Han, Adit D. Singh. 189-194 [doi]
- Single Test Clock with Programmable Clock Enable Constraints for Multi-clock Domain SoC ATPG TestingChin Hai Ang. 195-200 [doi]
- On the Generation of Compact Deterministic Test Sets for BIST Ready DesignsAmit Kumar, Janusz Rajski, Sudhakar M. Reddy, Thomas Rinderknecht. 201-206 [doi]
- A Cost-Effective Scheme for Network-on-Chip Router and Interconnect TestingDong Xiang. 207-212 [doi]
- Multi-histogram ADC BIST System for ADC Linearity TestingKoay Soon Chan, Nuzrul Fahmi Nordin, Kim Chon Chan, Terk Zyou Lok, Chee Wai Yong. 213-214 [doi]
- Fault Scrambling Techniques for Yield Enhancement of Embedded MemoriesShyue-Kung Lu, Hao-Cheng Jheng, Masaki Hashizume, Jiun-Lang Huang, Pony Ning. 215-220 [doi]
- Testing Disturbance Faults in Various NAND Flash MemoriesChih-Sheng Hou, Jin-Fu Li. 221-226 [doi]
- An Efficient Method for the Test of Embedded Memory Cores during the Operational PhasePaolo Bernardi, Lyl M. Ciganda, Matteo Sonza Reorda, Said Hamdioui. 227-232 [doi]
- Functional Test Generation at the RTL Using Swarm Intelligence and Bounded Model CheckingKelson Gent, Michael S. Hsiao. 233-238 [doi]
- Path Constraint Solving Based Test Generation for Hard-to-Reach StatesYanhong Zhou, Tiancheng Wang, Tao Lv, Huawei Li, Xiaowei Li 0001. 239-244 [doi]
- Accurate Multi-cycle ATPG in Presence of X-ValuesDominik Erb, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker. 245-250 [doi]
- Interplay of Failure Rate, Performance, and Test Cost in TCAM under Process VariationsHsunwei Hsiung, Da Cheng, Bin Liu 0004, Ramesh Govindan, Sandeep K. Gupta. 251-258 [doi]
- Critical Paths Selection and Test Cost Reduction Considering Process VariationsJifeng Chen, Mohammad Tehranipoor. 259-264 [doi]
- A Region-Based Framework for Design Feature Identification of Systematic Process VariationsShuo-You Hsu, Chih-Hsiang Hsu, Ting-Shuo Hsu, Jing-Jia Liou. 265-270 [doi]
- An Active Test Fixture Approach for 40 Gbps and Above At-Speed Testing Using a Standard ATE SystemJose Moreira, Bernhard Roth, Hubert Werkmann, Lars Klapproth, Michael Howieson, Mark Broman, Wend Ouedraogo, Mitchell Lin. 271-276 [doi]
- Enhanced Resolution Time-Domain Reflectometry for High Speed Channels: Characterizing Spatial Discontinuities with Non-ideal StimulusSuvadeep Banerjee, Hyun Woo Choi, David C. Keezer, Abhijit Chatterjee. 277-282 [doi]
- Time Domain Reconstruction of Incoherently Undersampled Periodic Waveforms Using Bandwidth InterleavingDebesh Bhatta, Nicholas Tzou, Sen-Wen Hsiao, Abhijit Chatterjee. 283-288 [doi]
- An Efficient Test Methodology for Image Processing Applications Based on Error-ToleranceTong-Yu Hsieh, Yi-Han Peng, Chia-Chi Ku. 289-294 [doi]
- Securing Access to Reconfigurable Scan NetworksRafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich. 295-300 [doi]
- A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D MemoriesWooheon Kang, Changwook Lee, Keewon Cho, Sungho Kang. 301-306 [doi]