Table of Contents

• Sustaining moore s law in embedded computing through probabilistic and approximate design: retrospects and prospectsKrishna V. Palem, Lakshmi N. Chakrapani, Zvi M. Kedem, Lingamneni Avinash, Kirthi Krishna Muntimadugu. 1-10 [doi]
• Complete nanowire crossbar framework optimized for the multi-spacer patterning techniqueM. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf Leblebici, Giovanni De Micheli. 11-16 [doi]
• Exploiting residue number system for power-efficient digital signal processing in embedded processorsRooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak. 19-28 [doi]
• Fast enumeration of maximal valid subgraphs for custom-instruction identificationTao Li, ZhiGang Sun, Wu Jigang, Xicheng Lu. 29-36 [doi]
• Hybrid multithreading for VLIW processorsManoj Gupta, Fermín Sánchez, Josep Llosa. 37-46 [doi]
• Spatial complexity of reversibly computable DAGMouad Bahi, Christine Eisenbeis. 47-56 [doi]
• Mapping stream programs onto heterogeneous multiprocessor systemsPaul M. Carpenter, Alex Ramírez, Eduard Ayguadé. 57-66 [doi]
• Optimal loop parallelization for maximizing iteration-level parallelismDuo Liu, Zili Shao, Meng Wang, Minyi Guo, Jingling Xue. 67-76 [doi]
• Progressive spill code placementDietmar Ebner, Bernhard Scholz, Andreas Krall. 77-86 [doi]
• Slicing based code parallelization for minimizing inter-processor communicationMahmut T. Kandemir, Yuanrui Zhang, Sai Prashanth Muralidhara, Ozcan Ozturk, Sri Hari Krishna Narayanan. 87-96 [doi]
• Fine-grain performance scaling of soft vector processorsPeter Yiannacouras, J. Gregory Steffan, Jonathan Rose. 97-106 [doi]
• Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGAYong Dou, Fei Xia, Jingfei Jiang. 107-116 [doi]
• Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructionsGaro Bournoutian, Alex Orailoglu. 117-126 [doi]
• Streaming FFT on REDEFINE-v2: an application-architecture design space explorationAlexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan. 127-136 [doi]
• A buffer replacement algorithm exploiting multi-chip parallelism in solid state disksJinho Seol, Hyotaek Shim, Jaegeuk Kim, Seungryoul Maeng. 137-146 [doi]
• Exposing non-standard architectures to embedded software using compile-time virtualisationIan Gray, Neil C. Audsley. 147-156 [doi]
• A platform for developing adaptable multicore applicationsDan Fay, Li Shang, Dirk Grunwald. 157-166 [doi]
• Parallel, hardware-supported interrupt handling in an event-triggered real-time operating systemFabian Scheler, Wanja Hofer, Benjamin Oechslein, Rudi Pfister, Wolfgang Schröder-Preikschat, Daniel Lohmann. 167-174 [doi]
• CheckerCore: enhancing an FPGA soft core to capture worst-case execution timesJin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang, Yuan Xie, Frank Mueller. 175-184 [doi]
• Instruction cache locking inside a binary rewriterKapil Anand, Rajeev Barua. 185-194 [doi]
• Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochipsElena Maftei, Paul Pop, Jan Madsen. 195-204 [doi]
• Tight WCRT analysis of synchronous C programsPartha S. Roop, Sidharta Andalam, Reinhard von Hanxleden, Simon Yuan, Claus Traulsen. 205-214 [doi]
• An accelerator-based wireless sensor network processor in 130nm CMOSMark Hempstead, Gu-Yeon Wei, David Brooks. 215-222 [doi]
• Smartphone-based assistive technologies for the blindPriya Narasimhan, Rajeev Gandhi, Dan Rossi. 223-232 [doi]
• OPAIMS: open architecture precision agriculture information monitoring systemYuexuan Wang, Yongcai Wang, Xiao Qi, Liwen Xu. 233-240 [doi]
• A case study of on-chip sensor network in multiprocessor system-on-chipYu Wang 0002, Jiang Xu, Shengxi Huang, Weichen Liu, Huazhong Yang. 241-250 [doi]
• A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi. 251-260 [doi]
• Towards scalable reliability frameworks for error prone CMPsJoseph Sloan, Rakesh Kumar. 261-270 [doi]
• CGRA express: accelerating execution using dynamic operation fusionYongjun Park, Hyunchul Park, Scott A. Mahlke. 271-280 [doi]
• Energy-aware probabilistic multiplier: design and analysisMark S. K. Lau, Keck Voon Ling, Yun-Chung Chu. 281-290 [doi]