Abstract is missing.
- Resistance of Randomized Projective Coordinates Against Power AnalysisWilliam Dupuy, Sébastien Kunz-Jacques. 1-14 [doi]
- Templates as Master KeysDakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi, Kai Schramm. 15-29 [doi]
- A Stochastic Model for Differential Side Channel CryptanalysisWerner Schindler, Kerstin Lemke, Christof Paar. 30-46 [doi]
- A New Baby-Step Giant-Step Algorithm and Some Applications to CryptanalysisJean-Sébastien Coron, David Lefranc, Guillaume Poupard. 47-60 [doi]
- Further Hidden Markov Model CryptanalysisP. J. Green, Richard Noad, Nigel P. Smart. 61-74 [doi]
- Energy-Efficient Software Implementation of Long Integer Modular ArithmeticJohann Großschädl, Roberto Maria Avanzi, Erkay Savas, Stefan Tillich. 75-90 [doi]
- Short Memory Scalar Multiplication on Koblitz CurvesKatsuyuki Okeya, Tsuyoshi Takagi, Camille Vuillaume. 91-105 [doi]
- Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µPLejla Batina, David Hwang, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede. 106-118 [doi]
- SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit IntegersJens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl, Christine Priplata, Colin Stahlke. 119-130 [doi]
- Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer FactorizationWilli Geiselmann, Adi Shamir, Rainer Steinwandt, Eran Tromer. 131-146 [doi]
- Design of Testable Random Bit GeneratorsMarco Bucci, Raimondo Luzzi. 147-156 [doi]
- Successfully Attacking Masked AES Hardware ImplementationsStefan Mangard, Norbert Pramstaller, Elisabeth Oswald. 157-171 [doi]
- Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing ConstraintsThomas Popp, Stefan Mangard. 172-186 [doi]
- Masking at Gate Level in the Presence of GlitchesWieland Fischer, Berndt M. Gammel. 187-200 [doi]
- Bipartite Modular MultiplicationMarcelo E. Kaihara, Naofumi Takagi. 201-210 [doi]
- Fast Truncated Multiplication for Cryptographic ApplicationsLaszlo Hars. 211-225 [doi]
- Using an RSA Accelerator for Modular InversionMartin Seysen. 226-236 [doi]
- Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite RingsBerk Sunar, David Cyganski. 237-249 [doi]
- EM Analysis of Rijndael and ECC on a Wireless Java-Based PDACatherine H. Gebotys, Simon Ho, C. C. Tiu. 250-264 [doi]
- Security Limits for Compromising EmanationsMarkus G. Kuhn. 265-279 [doi]
- Security Evaluation Against Electromagnetic Analysis at Design TimeHuiyun Li, A. Theodore Markettos, Simon W. Moore. 280-292 [doi]
- On Second-Order Differential Power AnalysisMarc Joye, Pascal Paillier, Berry Schoenmakers. 293-308 [doi]
- Improved Higher-Order Side-Channel Attacks with FPGA ExperimentsEric Peeters, François-Xavier Standaert, Nicolas Donckers, Jean-Jacques Quisquater. 309-323 [doi]
- Secure Data Management in Trusted ComputingUlrich Kühn, Klaus Kursawe, Stefan Lucks, Ahmad-Reza Sadeghi, Christian Stüble. 324-338 [doi]
- Data Remanence in Flash Memory DevicesSergei P. Skorobogatov. 339-353 [doi]
- Prototype IC with WDDL and Differential Routing - DPA Resistance AssessmentKris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede. 354-365 [doi]
- DPA Leakage Models for CMOS Logic CircuitsDaisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa. 366-382 [doi]
- The Backend Duplication MethodSylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet. 383-397 [doi]
- Hardware Acceleration of the Tate Pairing in Characteristic ThreePhilipp Grabher, Dan Page. 398-411 [doi]
- Efficient Hardware for the Tate Pairing Calculation in Characteristic ThreeTim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto. 412-426 [doi]
- AES on FPGA from the Fastest to the SmallestTim Good, Mohammed Benaissa. 427-440 [doi]
- A Very Compact S-Box for AESDavid Canright. 441-455 [doi]