Abstract is missing.
- Advances and challenges of computing with FPGAsJohn Wawrzynek. 1 [doi]
- Design challenges for prototypical and emerging memory concepts relying on resistance switchingChristophe Muller, Damien Deleruyelle, Olivier Ginez, Jean Michel Portal, Marc Bocquet. 1-7 [doi]
- All-digital 3-50 GHz ultra-wideband pulse generator for short-range wireless interconnect in 40nm CMOSChanghui Hu, Patrick Yin Chiang. 1-4 [doi]
- Band-gap circuit design challenges in high-performance 32-nm technologyJ. F. Buller, J. Fletcher, S. Meyers, M. Robinson, F. Tamayo, A. Prakash, D. Cabler. 1-4 [doi]
- A high gain 107 GHz amplifier in 130 nm CMOSOmeed Momeni, Ehsan Afshari. 1-4 [doi]
- A CMOS image sensor with on-chip motion detection and object localizationBo Zhao, Xiangyu Zhang, Shoushun Chen. 1-4 [doi]
- Design and technology interaction beyond 32nmMichael Clinton, Clive Bittlestone, G. Girishankar, Viet Le, Vinod Menezes. 1-9 [doi]
- A novel audio playback chip using digitally driven speaker architecture with 80%@-10dBFS power efficiency, 5.5W@3.3V supply and 100dB SNRMichitaka Yoshino, Mitsuhiro Iwaide, Daigo Kuniyoshi, Hajime Ohtani, Akira Yasuda, Jun-ichi Okamura. 1-4 [doi]
- A 2.2GHz PLL using a phase-frequency detector with an auxiliary sub-sampling phase detector for in-band noise suppressionChun-Wei Hsu, Karthik Tripurari, Shih-An Yu, Peter R. Kinget. 1-4 [doi]
- A sub-100µW 2GHz differential colpitts CMOS/FBAR VCOJianlei Shi, Brian P. Otis. 1-4 [doi]
- Energy efficient designs with wide dynamic rangeVivek De. 1 [doi]
- A capacitor-based AC-DC step-up converter for biomedical implantsEdward K. F. Lee. 1-4 [doi]
- A 65nm CMOS self-terminated open-drain IDAC line driver suitable for fast Ethernet applicationsJoseph N. Y. Aziz, Ark-Chew Wong, Andrew Chen, Derek Tam. 1-4 [doi]
- Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery networkPingqiang Zhou, Dong Jiao, Chris H. Kim, Sachin S. Sapatnekar. 1-4 [doi]
- A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nmPaul Merolla, John V. Arthur, Filipp Akopyan, Nabil Imam, Rajit Manohar, Dharmendra S. Modha. 1-4 [doi]
- Managing linearity in radio front-endsRanjit Gharpurey. 1-8 [doi]
- A near-zero cross-regulation single-inductor bipolar-output (SIBO) converter with an active-energy-correlation control for driving cholesteric-LCDYu-Huei Lee, Ming-Yan Fan, Wei-Chung Chen, Ke-Horng Chen, Sheng-Fa Liu, Pao-Hsien Chiu, Sandy Chen, Chun-Yu Shen, Ming-Ta Hsieh, Huai-An Li. 1-4 [doi]
- Bottom-up digital system-level reliability modelingN. Ruiz Amador, V. Huard, E. Pion, F. Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, L. Anghel. 1-4 [doi]
- SAW-less software-defined radio transceivers in 40nm CMOSJan Craninckx, Jonathan Borremans, Mark Ingels. 1-8 [doi]
- An all-digital PLL synthesized from a digital standard cell library in 65nm CMOSYoungmin Park, David D. Wentzloff. 1-4 [doi]
- Broadband compact model for on-chip mm-wave transformers and baluns with emphasis on capacitive coupling effectsYang Tang, Zuochang Ye, Yan Wang. 1-4 [doi]
- A transformer-based broadband I/O matching-balun-T/R switch front-end combo scheme in standard CMOSYanjie Wang, Hua Wang, Christopher D. Hull, Shmuel Ravid. 1-4 [doi]
- Power-efficient I/O design considerations for high-bandwidth applicationsJohn C. Eble, Scott Best, Brian S. Leibowitz, Lei Luo, Robert Palmer, John Wilson, Jared Zerbe, Amir Amirkhany, Nhat Nguyen. 1-8 [doi]
- A 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADCHo-Young Lee, David Gubbins, Bumha Lee, Un-Ku Moon. 1-4 [doi]
- A 60mW 1.15mA/channel Class-G Stereo Headphone Driver with 111dB DR and 120dB PSRRSherif Galal, Hui Zheng, Khaled Abdelfattah, Vinay Chandrasekhar, Iuri Mehr, Alex Jianzhong Chen, John Platenak, Nir Matalon, Todd Brooks. 1-4 [doi]
- A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion cancellerKohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka. 1-4 [doi]
- An at-speed self-testable technique for the high speed domino adderYu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Chi-Wei Liu, James Chien-Mo Li, Charlie Chung-Ping Chen. 1-4 [doi]
- Understanding the Antikythera MechanismTom Malzbender. 1 [doi]
- A 1-1-1-1 MASH delta-sigma modulator using dynamic comparator-based OTAsKentaro Yamamoto, Anthony Chan Carusone. 1-4 [doi]
- A 450 MS/s 10-bit time-interleaved zero-crossing based ADCJ. Chu, H. S. Lee. 1-4 [doi]
- Fast and accurate event-driven simulation of mixed-signal systems with data supplementationMyeong-Jae Park, Hanseok Kim, Minbok Lee, Jaeha Kim. 1-4 [doi]
- Timing inaccuracy of clocksAli Hajimiri. 1 [doi]
- Energy efficient computing in large scale systemsTajana Rosing. 1 [doi]
- A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizerSamira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez. 1-4 [doi]
- Overlapped inductors and its application on a shared RF front-end in a MultiStandard ICLei Feng, Ram Sadhwani, Yaron Peperovits, Christopher D. Hull, Jonathan Jensen. 1-4 [doi]
- A new CMOS image sensor readout structure for 3D integrated imagersShang-Fu Yeh, Jin-Yi Lin, Chih-Cheng Hsieh, Ka-Yi Yeh, Chung-Chi Jim Li. 1-4 [doi]
- 3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometryE. Ryman, A. Emrich, Stefan Andersson, J. Riesbeck, Lars J. Svensson, Per Larsson-Edefors. 1-4 [doi]
- High-dimensional statistical modeling and analysis of custom integrated circuits (invited paper)Trent McConaghy. 1-8 [doi]
- Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOSKangmin Hu, Tao Jiang, Samuel Palermo, Patrick Yin Chiang. 1-4 [doi]
- Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancyShunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto. 1-4 [doi]
- Double-balanced 130-180 GHz passive and balanced 145-165 GHz active mixers in 45 nm CMOSOzgur Inac, Andy Fung, Gabriel M. Rebeiz. 1-4 [doi]
- An open-loop 10GHz 8-phase clock generator in 65nm CMOSXiaochen Yang, Jin Liu. 1-4 [doi]
- ReSSP: A 5.877 TOPS/W Reconfigurable Smart-camera Stream ProcessorWei-Kai Chan, Yu-Hsiang Tseng, Pei-Kuei Tsung, Tzu-Der Chuang, Yi-Min Tsai, Wei-Yin Chen, Liang-Gee Chen, Shao-Yi Chien. 1-4 [doi]
- A non-coherent versatile DPSK receiver for high channel-density neural prosthesisLe Zheng, Kuanfu Chen, Wentai Liu. 1-4 [doi]
- Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOSMohamed H. Abu-Rahma, Ying Chen, Wing Sy, Wee Ling Ong, Leon Yeow Ting, Sei Seung Yoon, Michael Han, Esin Terzioglu. 1-4 [doi]
- Complete SOC transceiver in 0.18µm CMOS using Q-enhanced filtering, sub-sampling and injection lockingRalph Mason, Justin Fortier, Chris DeVries. 1-4 [doi]
- Ultra low-FOM high-precision ΔΣ modulators with fully-clocked SO and zero static power quantizersJian Xu, Xiaobo Wu, Menglian Zhao, Rui Fan, Hanqing Wang, Xiaofen Ma, Bill Liu. 1-4 [doi]
- A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applicationsTsung-Che Lu, Lan-Da Van, Chi-Sheng Lin, Chun-Ming Huang. 1-4 [doi]
- An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interfaceNavin K. Mishra, Manish Jain, Phuong Le, Sanku Mukherjee, Arul Sendhil, Amir Amirkhany. 1-4 [doi]
- High-efficient DC-DC converter designPhilip K. T. Mok. 1 [doi]
- A combined VCO and divide-by-two for low-voltage low-power 1.6 GHz quadrature signal generationShen Wang, Dong Sam Ha, Beomsup Kim, Vipul Chawla. 1-4 [doi]
- Addressing link-level design tradeoffs for integrated photonic interconnectsMichael Georgas, Jonathan Leu, Benjamin Moss, Chen Sun, Vladimir Stojanovic. 1-8 [doi]
- Zero-pole modulation and demodulation for noise reduction in charge amplifiersNasrin Jaffari, Katelijn Vleugels, Bruce A. Wooley. 1-4 [doi]
- Wafer-specific centering of compact transistor model parameters for advanced technologies and modelsB. de Vries, A. J. Scholten, P. F. E. Rommers, M. Stoutjesdijk, D. B. M. Klaassen. 1-4 [doi]
- 28nm metal-gate high-K CMOS SoC technology for high-performance mobile applicationsS.-H. Yang, J. Y. Sheu, M. K. Ieong, M.-H. Chiang, T. Yamamoto, J. J. Liaw, S. S. Chang, Y. M. Lin, T. L. Hsu, J. R. Hwang, J. K. Ting, C. H. Wu, K. C. Ting, F. C. Yang, C. M. Liu, I. L. Wu, Y. M. Chen, S. J. Chent, K. S. Chen, J. Y. Cheng, M.-H. Tsai, W. Chang, R. Chen, C. C. Chen, T. L. Lee, C. K. Lin, S. C. Yang, Y. M. Sheu, J. T. Tzeng, L. C. Lu, S. M. Jang, C. H. Diaz, Yuh-Jier Mii. 1-5 [doi]
- A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN applicationSanghyeon Lee, Jeongseok Chae, Mitsuru Aniya, Seiji Takeuchi, Koichi Hamashita, Pavan Kumar Hanumolu, Gabor C. Temes. 1-4 [doi]
- 2 with 700ps controller delay and network-on-chip load in 45-nm SOINoah Sturcken, Michele Petracca, Steve Warren, Luca P. Carloni, Angel V. Peterchev, Kenneth L. Shepard. 1-4 [doi]
- DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flowDragomir Milojevic, Herman Oprins, Julien Ryckaert, Paul Marchal, Geert Van der Plas. 1-4 [doi]
- A high-PSR LDO using a feedforward supply-noise cancellation techniqueBangda Yang, Brian Drost, Sachin Rao, Pavan Kumar Hanumolu. 1-4 [doi]
- Enhanced sensitivity computation for BEM based capacitance extraction using the Schur complement techniqueYu Bi, Simon de Graaf, Nick van der Meijs. 1-4 [doi]
- Analysis and modeling of on-chip power combiners and their losses in LINC transmittersAdil Koukab, Omid Talebi Amiri. 1-4 [doi]
- Fully integrated power-efficient AC-to-DC converter design in inductively-powered biomedical applicationsHyung-Min Lee, Maysam Ghovanloo. 1-8 [doi]
- A Low-Power and low-noise 21∼29 GHz ultra-wideband receiver front-end in 0.18 µm CMOS technologySheng-Li Huang, Yo-Sheng Lin, Jen-How Lee. 1-4 [doi]
- 0.4V SRAM with bit line swing suppression charge share hierarchical bit line schemeShinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano. 1-4 [doi]
- A dither-less all digital PLL for cellular transmittersLuca Vercesi, Luca Fanori, Fernando De Bernardinis, Antonio Liscidini, Rinaldo Castello. 1-8 [doi]
- A 0.6V quadrature VCO with optimized capacitive coupling for phase noise reductionFeng Zhao, Fa Foster Dai. 1-4 [doi]
- Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOSDavid Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Rick Wong. 1-4 [doi]
- A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technologyGautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Sergey V. Rylov, Troy J. Beukema, David Freitas, William Kelly, Michael Shannon, Jieming Qi, Hui H. Xu, Joseph Natonio, Todd M. Rasmus, Jong-Ru Guo, Michael Wielgos, Jon Garlett, Michael Sorna, Mounir Meghelli. 1-4 [doi]
- Circuit technologies for mm-wave wireless systems on siliconJohn R. Long, Yi Zhao, Y. Jin, Wanghua Wu, Marco Spirito. 1-8 [doi]
- Digital clock and data recovery circuit design: Challenges and tradeoffsMrunmay Talegaonkar, Rajesh Inti, Pavan Kumar Hanumolu. 1-8 [doi]
- Characterization and analysis of gate-all-around Si nanowire transistors for extreme scalingRu Huang, Runsheng Wang, Jing Zhuge, Changze Liu, Tao Yu, LiangLiang Zhang, Xin Huang, Yujie Ai, Jinbin Zou, Yuchao Liu, Jiewen Fan, Huailin Liao, Yangyuan Wang. 1-8 [doi]
- A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensationJa-Yol Lee, Mi-Jeong Park, Byonghoon Mhin, Seongdo Kim, Moon-Yang Park, Hyunku Yu. 1-4 [doi]
- A fully integrated CMOS nanoscale biosensor microarrayLei Zhang, Xiangqing He, Yan Wang, Zhiping Yu. 1-4 [doi]
- An 80% peak efficiency, 0.84mW sleep power consumption, fully-integrated DC-DC converter with buck/LDO mode controlXiaohan Gong, Jinhua Ni, Zhiliang Hong, Bill Liu. 1-4 [doi]
- Power management subsystem with bi-directional DC to DC converter for μ-power biomedical applicationsRaymond E. Barnett, Ganesh K. Balachandran. 1-4 [doi]
- Low power and error resilient PN code acquisition filter via statistical error compensationEric P. Kim, Daniel J. Baker, Sriram Narayanan, Douglas L. Jones, Naresh R. Shanbhag. 1-4 [doi]
- 5 Gbps BPSK CMOS transmitter with on-chip antenna using Gaussian monocycle pulsesShinichi Kubota, Nobuo Sasaki, Mohiuddin Hafiz, Akihiro Toya, Takamaro Kikkawa. 1-4 [doi]
- A passive UHF tag for RFID-based train axle temperature measurement systemJianqin Qian, Chun Zhang, Liji Wu, Xijin Zhao, Dingguo Wei, Zhihao Jiang, Yuhui He. 1-4 [doi]
- Smart integrated temperature sensor - mixed-signal circuits and systems in 32-nm and beyondY. William Li, Hasnain Lakdawala. 1-8 [doi]
- A quadrature LO generator using bidirectionally-coupled oscillators for 60-GHz applicationsMohammad Hekmat, David K. Su, Bruce A. Wooley. 1-4 [doi]
- Amorphous silicon current steering digital to analog converterAritra Dey, David R. Allee. 1-4 [doi]
- A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOSBiman Chattopadhyay, Anant S. Kamath, Satyasai Evani, Karthik Subburaj. 1-4 [doi]
- 0.5 -59.6dB THD dual-band micro-electrode array signal acquisition ICJing Guo, Jiageng Huang, George Jie Yuan, Jessica Ka-Yan Law, Chi-Kong Yeung, Mansun Chan. 1-4 [doi]
- 32-nm SOI programmable, high-bandwidth 8.0-GHz digital PLLSanjeev K. Maheshwari, Emerson S. Fang, Sanjeev Aggarwal. 1-4 [doi]
- Programmable phase/frequency generator for system debug and diagnosis using the IEEE 1149.1 test busTsung-Yen Tsai, Gordon W. Roberts. 1-4 [doi]
- A 2.9-dB noise figure, Q-band millimeter-wave CMOS SOI LNAMehmet Parlak, James F. Buckwalter. 1-4 [doi]
- A 7.4 Gb/s forwarded clock receiver based on first-harmonic injection-locked oscillator using AC coupled clock multiplication unit in 0.13µm CMOSYoung-Ju Kim, Sang-Hye Chung, Lee-Sup Kim. 1-4 [doi]
- A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOIMihai A. T. Sanduleanu, Scott K. Reynolds, Jean-Olivier Plouchart. 1-4 [doi]
- Test challenges for 3D integration (an invited paper for CICC 2011)W. R. Bottoms. 1-8 [doi]
- Frequency reference challenges - a systemic viewHarmeet Bhugra. 1 [doi]
- CDM-ESD induced damage in components using stacked-die packagingNicholas Olson, Nathan Jack, Vrashank Shukla, Elyse Rosenbaum. 1-4 [doi]
- A self-clocked ASIC interface for MEMS gyroscope with 1m°/s/√Hz noise floorA. Elsayed, A. Elshennawy, A. Elmallah, A. Shaban, B. George, M. Elmala, A. Ismail, A. Wassal, M. Sakr, A. Mokhtar, M. Hafez, A. Hamed, M. Saeed, M. Samir, M. Hammad, M. Elkhouly, A. Kamal, M. Rabieah, A. Elghufaili, S. Shaibani, I. Hakami, T. Alanazi. 1-4 [doi]
- Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMsYasumasa Tsukamoto, Takeshi Kida, T. Yamaki, Yuichiro Ishii, Koji Nii, Koji Tanaka, Shinji Tanaka, Yuji Kihara. 1-4 [doi]
- Silicon photonics for on-chip interconnectionsAlan Rolf Mickelson. 1-8 [doi]
- Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIsAkira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi. 1-7 [doi]
- A discrete-time charge-domain filter with bandwidth calibration for LTE applicationMing-Feng Huang. 1-4 [doi]
- Power gating implementation for noise mitigation with body-tied triple-well structureYasumichi Takai, Masanori Hashimoto, Takao Onoye. 1-4 [doi]
- A wireless sensor node for condition monitoring powered by a vibration energy harvesterJae-Hyuk Jang, David F. Berdy, Jangjoon Lee, Dimitrios Peroulis, Byunghoo Jung. 1-4 [doi]
- A partial tree vector quantizer dynamic element matching technique for audio Δ-Σ convertersEmmanuel Hardy, Hassan Ihs, Christian Dufaza, Stéphane Meillére, Rachid Bouchakour. 1-4 [doi]
- Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETsToshiro Hiramoto, Anil Kumar, Tomoko Mizutani, Jun Nishimura, Takuya Saraya. 1-4 [doi]
- Perturbation on-time (POT) control and inhibit time control (ITC) in suppression of THD of power factor correction (PFC) designJen-Chieh Tsai, Chi-Lin Chen, Yi-Ting Chen, Chia-Lung Ni, Chun-Yen Chen, Ke-Horng Chen, Chih-Jen Chen, Heng-Lin Pan. 1-4 [doi]
- nd order digital compensation and direct battery connection in 40nm CMOSJustin Shi, Ying-Chih Hsu, Eric G. Soenen, Alan Roth, Justin Gaither. 1-4 [doi]
- A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognitionGuangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 1-4 [doi]
- An 80% peak efficiency, 410mW, single supply rail powered Class-I linear audio amplifierZhenfei Peng, Shanshan Yang, Yong Feng, Zhiliang Hong, Bill Liu. 1-4 [doi]
- A 1V 13mW frequency-translating ΔΣ ADC with 55dB SNDR for a 4MHz band at 225MHzPhilip M. Chopp, Anas A. Hamoui. 1-4 [doi]
- Indirect phase noise sensing for self-healing voltage controlled oscillatorsSoner Yaldiz, V. Calayir, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, José A. Tierno. 1-4 [doi]
- Three Dimensional integration - Considerations for memory applicationsSubramanian S. Iyer, Toshiaki Kirihata, John E. Barth Jr.. 1-7 [doi]
- A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOSBei Peng, Guanzhong Huang, Hao Li 0001, Peiyuan Wan, Pingfen Lin. 1-4 [doi]
- Thermal diffusivity sensing: A new temperature sensing paradigmCaspar P. L. van Vroonhoven, Kofi A. A. Makinwa. 1-6 [doi]
- A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysisPeiyuan Wang, Xiang Chen, Yiran Chen, Hai Helen Li, Seung H. Kang, Xiaochun Zhu, Wenqing Wu. 1-4 [doi]
- CMOS field-modulated color sensorDerek Ho, P. Glenn Gulak, Roman Genov. 1-4 [doi]
- A reconfigurable 2× / 2.5× / 3× / 4× SC DC-DC regulator for enhancing area and power efficiencies in transcutaneous power transmissionXiwen Zhang, Hoi Lee. 1-4 [doi]
- A monolithic 3.125 Gbps fiber optic receiver front-end for POF applications in 65 nm CMOSYunzhi Dong, Kenneth W. Martin. 1-4 [doi]
- A 3.6GS/s, 15mW, 50dB SNDR, 28MHz bandwidth RF ΔΣ ADC with a FoM of 1pJ/bit in 130nm CMOSAhmed Ashry, Hassan Aboushady. 1-4 [doi]
- A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOSI.-Ning Ku, Zhiwei Xu, Yen-Cheng Kuan, Yen-Hsiang Wang, Mau-Chung Frank Chang. 1-4 [doi]
- A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOSNan Qi, Yang Xu, Baoyong Chi, Yang Xu, Xiaobao Yu, Xing Zhang, Zhihua Wang. 1-4 [doi]
- A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mWRamin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez. 1-4 [doi]
- Electrically-driven retargeting for nanoscale layoutsShayak Banerjee, Kanak B. Agarwal, Sani R. Nassif. 1-4 [doi]
- 256-site active neural probe and 64-channel responsive cortical stimulatorRuslana Shulyzki, Karim Abdelhalim, A. Bagheri, C. M. Florez, Peter L. Carlen, Roman Genov. 1-4 [doi]
- A 90nm data flow processor demonstrating fine grained DVS for energy efficient operation from 0.25V to 1.2VYousef Shakhsheer, Sudhanshu Khanna, Kyle Craig, Saad Arrabi, John Lach, Benton H. Calhoun. 1-4 [doi]
- A 19 mW/lane Serdes transceiver for SFI-5.1 applicationSiavash Fallahi, Delong Cui, Deyi Pi, Rose Zhu, Greg Unruh, Marcel Lugthart, Afshin Momtaz. 1-4 [doi]
- A fully-integrated optical duobinary transceiver in a 130nm SOI CMOS technologyJames F. Buckwalter, Joohwa Kim, Xuezhe Zheng, Guoliang Li, Kannan Raj, Ashok V. Krishnamoorthy. 1-4 [doi]
- A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neuronsJae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman. 1-4 [doi]
- Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAMKousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano, Ken Takeuchi. 1-4 [doi]
- A true single SoC for UHF mobile RFID readerJongmoon Kim, Seokoh Yun, Wonkab Oh, Minsu Kil, Sanghyun Cho. 1-4 [doi]
- A low conversion loss passive frequency doublerMuhammad Adnan, Ehsan Afshari. 1-4 [doi]
- A multi-GHz area-efficient comparator with dynamic offset cancellationLingkai Kong, Yue Lu, Elad Alon. 1-4 [doi]
- Improved circuits for microchip identification using SRAM mismatchSrivatsan Chellappa, Aritra Dey, Lawrence T. Clark. 1-4 [doi]
- A 0.5-V, 440-µW frequency synthesizer for implantable medical devicesWu-Hsin Chen, Wing-Fai Loke, Gabriel J. Thompson, Byunghoo Jung. 1-4 [doi]
- An 18µW 79dB-DR 20KHz-BW MASH ΔΣ modulator utilizing self-biased amplifiers for biomedical applicationsLe Wang, Luke Theogarajan. 1-4 [doi]
- Energy-efficient transceiver circuits for short-range on-chip interconnectsJacob Postman, Patrick Chiang. 1-4 [doi]
- A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delayVikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, Debasish Behera. 1-4 [doi]
- A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source biasY. Umemoto, Koji Nii, J. Ishikawa, Kazuyoshi Okamoto, K. Mori, K. Yanagisawa. 1-4 [doi]
- A time-domain latch interpolation technique for low power flash ADCsJong-In Kim, Wan Kim, Barosaim Sung, Seung-Tak Ryu. 1-4 [doi]
- A 20 µW contact impedance sensor for wireless body-area-network transceiverKiseok Song, Joonsung Bae, Long Yan, Hoi-Jun Yoo. 1-4 [doi]
- Area efficient phase calibration of a 1.6 GHz multiphase DLLAnkur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei. 1-4 [doi]
- A 76-81GHz transmitter with 10dBm output power at 125 °C for automotive radar in 65nm bulk CMOSKun-Hin To, Vishal P. Trivedi. 1-4 [doi]
- A fully integrated highly linear efficient power amplifier in 0.25µm BiCMOS technology for wireless applicationsHajir Hedayati, Mohamed Mobarak, Guillaume Varin, Philippe Meunier, Patrice Gamand, Edgar Sánchez-Sinencio, Kamran Entesari. 1-4 [doi]
- A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLLPyoungwon Park, Dongmin Park, SeongHwan Cho. 1-4 [doi]
- A 95dB SNDR audio ΔΣ modulator in 65nm CMOSL. Liu, D. Li, Y. Ye, L. Chen, Z. Wang. 1-4 [doi]
- Noise and bandwidth performance of single-molecule biosensorsJacob Rosenstein, Sebastian Sorgenfrei, Kenneth L. Shepard. 1-7 [doi]
- 60GHz low-loss compact phase shifters using a transformer-based hybrid in 65nm CMOSMaryam Tabesh, Amin Arbabian, Ali M. Niknejad. 1-4 [doi]