Table of Contents

• An Integrated Burst-Mode 2R Receiver Employing Fast Residual Offset Canceller for XGS-PON in 40-nm CMOSYifei Xia, Shuaizhe Ma, Wanqing Zhao, Jia Li, Ruixuan Yang, Yuye Yano, Xi Liu, Feiyang Zhang, Jianyu Yang, Wenbo Shi, Lei Jing, Xiaoyan Gui, Bing Zhang, Li Geng, Dan Li 0011. 1-2 [doi]
• A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-DetectorSimone Mattia Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino. 1-2 [doi]
• A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIRHeyu Ren, Liangjian Lyu, Binbin Chen, Chuanjin Richard Shi. 1-2 [doi]
• Scalable and Interpretable Brain-Inspired Hyper-Dimensional Computing Intelligence with Hardware-Software Co-DesignHanning Chen, Yang Ni 0001, Wenjun Huang, Mohsen Imani. 1-8 [doi]
• 52.5 TOPS/W 1.7GHz Reconfigurable XGBoost Inference Accelerator Based on Modular-Unit-Tree with Dynamic Data and Compute GatingChang Eun Song, Yidong Li, Amardeep Ramnani, Pulkit Agrawal 0003, Purvi Agrawal, Sung-Joon Jang, Sang-Seol Lee, Tajana Rosing, Mingu Kang. 1-2 [doi]
• A 3.3-to-11V-Supply-Range 10μW/Ch Arbitrary-Waveform-Capable Neural Stimulator with Output-Adaptive-Self-Bias and Supply-Tracking Schemes in 0.18μm Standard CMOSJeongyoon Wie, Sangwoo Jung, Taeryoung Seol, Geunha Kim, Sehwan Lee, Homin Jang, Samhwan Kim, Yeonjae Shin, Jae Eun Jang, Jaeha Kung, Arup K. George, Junghyup Lee. 1-2 [doi]
• An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoMYu He, Xuqiang Zhenq, Zedong Wang, Zunsong Yanq, Hua Xu, Fangxu Lv, Mingche Lai, Xinyu Liu. 1-2 [doi]
• ASIL-D and AEC-Q100 Grade 0 Compliant Automotive RC Oscillator with Farey Sequence-based CalibrationJeongwon Ham, Won-Jong Choi, Young-Suk Son, Sang-Gug Lee 0001, Kyeongha Kwon. 1-2 [doi]
• A 65nm and 130nm CMOS Programmable Analog Standard Cell Library for Scalable System SynthesisPranav O. Mathews, Praveen Raj Ayyappan, Afolabi Ige, Swagat Bhattacharyya, Linhao Yang, Jennifer Hasler. 1-2 [doi]
• A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOSKai Li 0024, Hantao Huang, Mingqiang Huang, Chenchen Ding, Longyang Lin, Liebing Ni, Hao Yu 0001. 1-2 [doi]
• A 128Gb/s PAM-4 Transmitter with Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28nm CMOSHongzhi Wu, Weitao Wu, Liping Zhong, Xuxu Cheng, Yangyi Zhang 0002, Xiongshi Luo, Dongfan Xu, Xindan Yu, Quan Pan 0002. 1-2 [doi]
• 212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter VariationXinyu Shen, Zhao Zhang 0004, Yong Chen 0005, Yixi Li, Yidan Zhang, Guike Li, Nan Qi 0002, Jian Liu 0021, Nanjian Wu, Liyuan Liu. 1-2 [doi]
• 2 Floating-Point SRAM-Based Digital Computing-in-Memory Macro in 28-nm CMOSChuan-Tung Lin, Jonghyun Oh, Kevin Lee, Mingoo Seok. 1-2 [doi]
• A 73.3% Peak Efficiency Isolated DC-DC Converter with Gap-Time Modulation using Pseudo-Hysteresis Control for -12kV/μs Common-Mode Transient ImmunityYang Liu, Yuan Yao, Lin Cheng 0001, Wing-Hung Ki. 1-2 [doi]
• A 56-Gbaud 7.3-Vppd Linear Modulator Transmitter with AMUX-Based Reconfigurable FFE and Dynamic Triple-Stacked Driver in 130-nm SiGe BiCMOSFuzhan Chen, C. Patrick Yue, Quan Pan 0002. 1-2 [doi]
• A Saturation-Free 3.6V/1.8V DM/CM Input Range 46.6mV/μs Artifacts Recovery Sensor Interface using CT Track-and-ZoomQiao Cai, Xinzi Xu, Yanxing Suo, Guanghua Qian, Yongfu Li 0002, Guoxing Wang, Yong Lian 0001, Yang Zhao 0007. 1-2 [doi]
• A Monolithic 3-Level Single-Inductor Multiple-Output Buck Converter with State-Based Non-Linear Control Capable of Handling 1A/1.5ns Transient with On-Die LCJunyao Tang, Jianqiang Jiang, Lei Zhao, Xin Zhang 0025, Kang Wei, Cheng Huang 0004. 1-2 [doi]
• Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and CalibrationTimothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli. 1-8 [doi]
• A 0.078 pJ/SOP Unstructured Sparsity-Aware Spiking Attention/Convolution Processor with 3D Compute ArrayChaoming Fang, Ziyang Shen, Shiqi Zhao, Chuanqing Wang, Fengshi Tian, Jie Yang 0033, Mohamad Sawan. 1-2 [doi]
• A Pseudo-Adiabatic Switched-Capacitor Gate Driver for Si and GaN FETs Achieving >5x Power ReductionYanqiao Li, Ziyu Xia, Jason T. Stauth. 1-2 [doi]
• A Mm-Wave Phase-Time Co-Apertured Transceiver Array with Beam Squinting Mitigation for Wideband Beamforming/Spatial-NullingMohamed Eleraky, Jeongsoo Park 0006, Basem Abdelaziz Abdelmagid, Naga Sasikanth Mannem, Hua Wang 0006. 1-2 [doi]
• A 0.25pJ/Comparison, 27.3μV Input Noise Dynamic Comparator Exploiting Stacked Floating Preamplifier with Cross-Coupled Feedback Inverters in 180nm CMOSJiangchao Wu, Ke Hu, Xuanlin Chen, Pui-In Mak, Rui Paulo Martins, Man Kay Law. 1-2 [doi]
• A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset CalibrationWenning Jiang, Yunbin Luo, Peizhe Li, Ji Guo, Chixiao Chen, Qi Liu 0010. 1-2 [doi]
• A Beamforming Receiver Using a Time-Modulated LO-Path Vector Modulator Achieving Amplitude and Phase Control with 0.2 dB RMS Gain Error and 1.4 Degree RMS Phase ErrorPetar Barac, Matthew Bajor, Tanbir Haque, Peter R. Kinget. 1-2 [doi]
• A 18.2mW Subsampling mm-Wave Receiver Employing a Subtractive Anti-Aliasing Active Bandstop Filter at 23GHzAhmed G. Gadelkarim, Patrick P. Mercier. 1-2 [doi]
• A 737nA Always-On MEMS Gyroscope with 5.45ms Start-up Time Using Burst Mode PLL TechniqueLongjie Zhong, Chengyue Li, Shubin Liu 0001, Mingsheng Zhong, Zhangming Zhu. 1-2 [doi]
• A 188.6-μW Continuous-time Incremental Delta-Sigma ADC with Extended Counting achieving 95.2-dB SNDR and 175.4-dB FoMSNDRZhaonan Lu, Menglian Zhao, Zhichao Tan. 1-2 [doi]
• A 1.58-nA CEPE-Based Hill-Climbing MPPT Technique with Compensated Ton Achieving 67.3% Efficiency at 10-nA Lload and > 97% MPPT Efficiency at VCR from 2 to 6Qiujin Chen, Tian Xia, Tingxu Hu, Yuanfei Wang, Mo Huang, Rui Paulo Martins, Yan Lu 0002. 1-2 [doi]
• A 2λ×100 Gb/s Optical Receiver with Si-Photonic Micro-Ring Resonator and Photo-Detector for DWDM Optical-IOSikai Chen, Jintao Xue, Yihan Chen, Yuean Gu, Haoran Yin, Shenlei Bao, Guike Li, Binhao Wang, Nan Qi. 1-2 [doi]
• 2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAMGuodong Yin, Yiming Chen, Mingyen Lee, Xirui Du, Yue Ke, Wenjun Tang, Zhonghao Chen, Mufeng Zhou, Jinshan Yue, Huazhong Yang, Hongyang Jia, Yongpan Liu, Xueqing Li 0002. 1-2 [doi]
• A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing AttacksMaitreyi Ashok, Saurav Maji, Xin Zhang 0025, John Cohn, Anantha P. Chandrakasan. 1-2 [doi]
• A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass QuantizerJing Jin 0005, Yuekang Guo, Meng Xu, Xiaoming Liu 0008, Nan Sun, Jianjun Zhou. 1-2 [doi]
• A 20-24-GHz DPSSPLL with Charge-Domain Bandwidth Optimization Scheme Achieving 61.3-fs RMS Jitter and -253-dB FoMJitterLi Wang, Zilu Liu, Ruitao Ma, C. Patrick Yue. 1-2 [doi]
• A 96.7%-Efficient 2.5A Scalable DC-DC Converter Module with Complementary Dual-Mode Reconfigurable Hybrid Topology Achieving Always Inductor Current Reduction, Continuously Adjustable VCR Range, and Interleaving COUT AugmentationHuihua Li, Qiaobo Ma, Yang Jiang 0002, Rui Paulo Martins, Pui-In Mak. 1-2 [doi]
• A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band OperationZilong Shen, Jiaiun Tang, Haoyang Luo, Zhongyi Wu, Zongnan Wang, Xing Zhang 0002, Xiyuan Tang, Yuan Wang 0001. 1-2 [doi]
• A 40nm 1.26µ/Op Energy-Efficient CRYSTALS-KYBER Post-Quantum Crypto-Processor with Comprehensive Side Channel Security Analysis and CountermeasuresAobo Li, Jiahao Lu, Dongsheng Liu, Xiang Li. 1-2 [doi]
• A Fast-Slow Two-Module DC-DC Solution with Transient and Efficiency Improvements for 2.5D/3D IntegrationJunwei Huang, Zhiguo Tong, Xiangyu Mao, Chi-Seng Lam, Rui Paulo Martins, Yan Lu 0002. 1-2 [doi]
• An 80MS/s 70.79dB-SNDR 60.7fJ/Conv-Step Radiation-Tolerant Semi-Time-interleaved Pipelined-SAR ADCZheyi Li, Laurent Berti, Qiuyang Lin, Jinghao Zhao, Maxim Gorbunov, Geert Thys, Paul Leroux. 1-2 [doi]
• Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less DataflowYikan Qiu, Yufei Ma 0002, Meng Wu, Yifan Jia 0009, Xinyu Qu, Zecheng Zhou, Jincheng Lou, Tianyu Jia, Le Ye, Ru Huang 0001. 1-2 [doi]
• A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADCPengyu He, Yuanzhe Zhao, Heng Xie, Yang Wang, Shouyi Yin, Li Li, Yan Zhu 0001, Rui Paulo Martins, Chi-Hang Chan, Minglei Zhang. 1-2 [doi]
• BEE-SLAM: A 65nm 17.96 TOPS/W 97.55%-Sparse-Activity Hybrid Mixed-Signal/Digital Multi-Agent Neuromorphic SLAM Accelerator for Swarm RoboticsJaeHyun Lee, Dong Gu Choi, Minyoung Song, Gain Kim, Jong-Hyeok Yoon. 1-2 [doi]
• The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCsChi-Hang Chan, Minglei Zhang, Yuefena Cao, Honazhi Zhao, Rui Paulo Martins, Yan Zhu 0001. 1-8 [doi]
• A 12V-to-PoL CCC-Based Easy-Scalable Multiple-Phase Hybrid Converter with Auto VCF Balancing and Inactive CF ChargingJiacheng Yang, Tingxu Hu, Mo Huang, Rui Paulo Martins, Yan Lu 0002. 1-2 [doi]
• An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist InputJie Li, Linxiao Shen, Siyuan Ye, Jihang Gao, Jiajia Cui, Xinhang Xu, Zhuoyi Chen, Yaohui Luan, Yuanxin Bao, Ru Huang 0001, Le Ye. 1-2 [doi]
• A 103.6dB-SNDR 760mVPP-Input-Range 7.8GΩ-Input-Impedance Direct-Digitization Sensor Readout with Pseudo-Differential Transconductors and Dummy DACJianhong Zhou, Yijie Li, Kaiwen Zhou, Yuying Li, Tian Dong, Zhiliang Hong, Jiawei Xu 0001. 1-2 [doi]
• A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNsZhaoyang Zhang, Zhichao Liu, Feiran Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Xingyu Pu, Xing Wang, Jun Yang 0006, Xin Si. 1-2 [doi]
• A Closed-Loop Brain-Machine Interface SoC Featuring a 0.2μJ/class Multiplexer Based Neural NetworkChao Zhang 0075, Yongxiang Guo, Dawid Sheng, Zhixiong Ma, Chao Sun, Yuwei Zhang 0012, Wenxin Zhao, Fenyan Zhang, Tongfei Wang, Xing-sheng, Milin Zhang 0001. 1-2 [doi]
• A 1-TFLOPS/W, 28-nm Deep Neural Network Accelerator Featuring Online Compression and Decompression and BF16 Digital In-Memory-Computing HardwareBo Zhang, SeungHyun Moon, Mingoo Seok. 1-2 [doi]
• A 50MHz-BW 168.8dB-FoM 2x Time-Interleaved Bandpass Noise Shaping SAR ADC Using Passive FilterSeungjun Song, Dongsik Lee, Hyungil Chae. 1-2 [doi]
• A Quad-Output Hybrid Buck Converter with 8-Inductor Helping One Spot from All Quarters for Multi-Core XPUsXiangyu Mao, Junwei Huang, Zhiguo Tong, Rui Paulo Martins, Yan Lu 0002. 1-2 [doi]
• A Co-Integrated Optical Phased Array, Mach-Zehnder Modulator and Mm-Wave Driver for Free-Space CommunicationYoungin Kim 0001, Laurenz Kulmer, Killian Keller, Jeongsoo Park 0006, Basem Abdelaziz Abdelmagid, Kyung-Sik Choi, Dongwon Lee, Yuqi Liu, Juerg Leuthold, Hua Wang 0006. 1-2 [doi]
• A 75dB-SNDR 10MHz-BW 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by an On-Chip DC-DC ConverterHaoyu Gong, Wen-Liang Zeng, Mingqiang Guo, Chi-Seng Lam, Shulin Zhao 0004, Rui Paulo Martins, Sai-Weng Sin. 1-2 [doi]
• A 7V/μs-DVS Class-G Digital-Shunt-Aided Buck Voltage Regulator Achieving a 7% Dynamic-Efficiency Drop at a 600kHz DVS Occurrence Frequency in 28nm CMOSHong-Hyun Bae, Jeong-Hyun Cho, Kihyun Kim, Seunghwa Shin, Doojin Jang, Jun Hyeok Yang, Hyun-Sik Kim. 1-2 [doi]
• A Cryogenic Double-IF SSB Controller with Image Suppression and On-Chip Filtering implemented in 130nm SiGe BiCMOS Technology for Superconducting Qubit ControlYatao Peng, Jad Benserhir, Yating Zou, Edoardo Charbon. 1-2 [doi]
• 131TOPS/W 8b ACIM Exploiting Weight-Embedded Auto-Accumulation and Supporting Symmetric Quantization NetworksWei He, Puvi Bai, Hongyang Luo, Zhenghao Jin, Han Wu, Junyi Zhang, Xingchen Chao, Haiqi Liu, Yajuan He, Qiang Li 0021. 1-2 [doi]
• A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOSXinyu Qin, Yichen Jin, Guoxing Wang, Sai-Weng Sin, Maurits Ortmanns, Yong Lian 0001, Liang Qi 0002. 1-2 [doi]
• CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming ProblemsMengtian Yang, Yipeng Wang 0017, Shanshan Xie, Chieh-Pu Lo, Meizhi Wang, Sirish Oruganti, Rishabh Sehgal, Jaydeep P. Kulkarni. 1-2 [doi]
• A 99.4 dB SFDR 91.9 dB DR Continuous-Time Incremental Delta-Sigma ADC with a Noise-Shaping SAR Quantizer and a Passive Input Feedforward Stabilization PathCheng-En Wei, Shih-Che Kuo, Chia-Hung Chen. 1-2 [doi]
• An 871nW 96.2dB-SNDR Pipelined NS SAR ADC Achieving 180.8dB-FoMSNDR with a Charge-Efficient CLS-Assisted Two-Stage FIAShan Zhang, Lingxin Meng, Zhaonan Lu, Wanyuan Qu, Shuang Song 0003, Menglian Zhao, Zhichao Tan. 1-2 [doi]
• A 16MHz CMOS RC Frequency Reference with ±125ppm Inaccuracy from -40°C to 85°C Enabled by a Capacitively Modulated RC Time Constant (CMT) Generation and a Die-to-Die Error Removal (DDER) TechniqueRuntao Huo, Dingguo Zhang, Jing Jin 0005, Jianjun Zhou, Hui Wang. 1-2 [doi]
• Challenges and Innovations in Fully Integrated DC-DC Converters for IoT and Modern Computing PlatformsSuyang Song, Alessandro Novello, Taekwang Jang. 1-8 [doi]
• A 63ns Flipping Time, 93.6% Voltage Flipping Efficiency Auto-Calibrated Ultrasonic Energy Harvesting Interface from -25 to 85°CGuangshu Zhao, Chao Xie, Chenxi Wang, Yang Jiang 0002, Milin Zhang 0001, Pui-In Mak, Rui Paulo Martins, Man Kay Law. 1-2 [doi]
• A PVT-Robust 8b 20GS/s Time-Interleaved SAR ADC with Quantization-Embedded Current-Mode Buffer and Differ-Based Dither Timing Skew CalibrationWei Zhang, Minglei Zhang, Yan Zhu 0001, R. P. Martins, Chi-Hang Chan. 1-2 [doi]
• A 2.5-20kSps in-Pixel Direct Digitization Front-End for ECoG with In-Stimulation RecordingAditi Jain, Eric Fogleman, Paul Botros, Ritwik Vatsyayan, Corentin Pochet, Andrew Bourhis, Zhaoyi Liu, Suhas Chethan, Hanh-Phuc Le, Ian Galton, Shadi A. Dayeh, Drew A. Hall. 1-2 [doi]
• A 28nm 1.2GHz 5.27TOPS/W Scalable Vision/Point Cloud Deep Fusion Processor with CAM-based Universal Mapping Unit for BEVFusion ApplicationsXiaoyu Feng, Wenyu Sun, Xinyuan Lin, Shupei Fan, Huazhong Yang, Yongpan Liu. 1-2 [doi]
• Advanced Sensing Systems Exploiting the Integration of Flexible and Large-Area TFTs with Si-CMOS TechnologyMarco Fattori, Enrico Genco, Carmine Garripoli, Mohammad Zulqarnain, Kris Myny, Eugenio Cantatore. 1-8 [doi]
• Intelligent Neural Interfaces: An Emerging Era in NeurotechnologyMahsa Shoaran, Uisub Shin, Mohammad Ali Shaeri. 1-7 [doi]
• A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-FilteringKe Li, Xianyu Congzhou, Liang Qi, Mingqiang Guo, Rui Paulo Martins, Sai-Weng Sin. 1-2 [doi]
• A 16b 5MS/s 93.7dB-SNDR SAR ADC with a Split Sampling Technique and SRM-Assisted Self-CalibrationQifeng Huang, Siji Huang, Yanhang Chen, Yifei Fan, Jie Yuan. 1-2 [doi]
• A Wireless Subdural Optical Cortical Interface Device with 768 Co-Packaged Micro-LEDs for Fluorescence Imaging and Optogenetic StimulationYatin Gilhotra, Henry Overhauser, Heyu Yin, Eric H. Pollmann, Guy Eichler, Andrew Cheng, Taesung Jung, Nanyu Zeng, Luca P. Carloni, Kenneth L. Shepard. 1-2 [doi]
• A 10V Compliant 16-Channel Stimulator ASIC with sub-10nA Mismatch and Simultaneous ETI Sensing for Selective Vagus Nerve StimulationHaoming Xin, Meiyi Zhou, Roland Van Wegberg, Peter Vis, Konstantinos Petkos, Shrishail Patki, Nicolò Rossetti, Mark Fichman, Vojkan Mihajlovic, Carolina Mora Lopez, Geert Langereis, Mario Konijnenburg, Nick Van Helleputte. 1-2 [doi]
• A 6.8-to-14.4GHz Octave-Tuning Fractional-N Charge-Pump PLL with Slide-Dithering-Based Background DTC Nonlinearity Calibration for Near-Integer Fractional Spur Mitigation Achieving 78fs RMS Jitter and -258.6dB $\text{FoM}_{\mathrm{T}}$Zonglin Ye, Xinlin Geng, Zhixiang Shi, Hongyang Zhang, Qian Xie 0002, Zheng Wang 0050. 1-2 [doi]
• A 28nm All-Digital Droop Detection and Mitigation Circuit Using a Shared Dual-Mode Delay Line with 14.8% VminReduction and 42.9% Throughput GainMinyoung Kang, Sunghoon Kim, Youngmin Park, Sangsu Jeong, Dongsuk Jeon. 1-2 [doi]
• A 24.4μW Room Temperature Gas Sensor Based on Molecularly Imprinted Polymers Demonstrating SARS-Cov-2 and D-Glucose Aerosol SensingRyan Burns, Austin Wiechmann, Pardis Sadeghi, Nader Lobandi, Nader Fathy, Rui Huang, Nian Sun, Patrick P. Mercier. 1-2 [doi]
• Silicon Photonics Chip I/O for Ultra High-Bandwidth and Energy-Efficient Die-to-Die ConnectivityYuyang Wang 0003, Songli Wang, Robert Parsons, Asher Novick, Vignesh Gopal, Kaylx Jang, Anthony Rizzo, Chia-Pin Chiu, Kaveh Hosseini, Tim Tri Hoang, Sergey Y. Shumarayev, Keren Bergman. 1-8 [doi]
• SP-IMC: A Sparsity Aware In-Memory-Computing Macro in 28nm CMOS with Configurable Sparse Representation for Highly Sparse DNN WorkloadsAmitesh Sridharan, Fan Zhang 0069, Jae-sun Seo, Deliang Fan. 1-2 [doi]
• A 65nm 3mA 0.14-m-Accuracy TDR Based Leak Detection SoC for District Heating Networks with I/C Calibration TechniqueYarallah Koolivand, Alireza Mosalmani, Yasser Rezaeiyan, Hossein Esmailbeygi, Elham Hatamzadeh, Milad Zamani, Farshad Moradi. 1-2 [doi]
• A Tri-Mode Filtering Power Amplifier for 5G Millimeter-Wave Dual-Side LO Injection Systems with Power-Efficiency EnhancementWeisen Zeng, Li Gao, Hui-Yang Li, Jin-Xu Xu, Hongtao Xu, Xiu Yin Zhang. 1-2 [doi]
• A 7.9 ps Resolution, Multi-Event TDC Using an Ultra-Low Static Phase Error DLL and High Linearity Time Amplifier for dToF SensorsXiayu Wang, Zhaoyang Zhou, ChunLin Li, Jin Hu 0006, Dong Li, Rui Ma 0007, Yang Liu 0106, Zhangming Zhu. 1-2 [doi]
• 2-1.38μW/Ch Wireless Implantable Neural Interface with Direct Multiplexing Front-End and Event-Driven Spike Detection and TransmissionJinbo Chen, Hui Wu, Razieh Eskandari, Xing Liu, Siyu Lin, Qiming Hou, Fengshi Tian, Wenjun Zou, Jie Yang 0033, Mohamad Sawan. 1-2 [doi]
• 2 Fully Integrated, 1.5m Transmission-Range, High-Data-Rate IR-UWB Transmitter for Brain ImplantsCong Ding 0004, Mingxiang Gao, Anja K. Skrivervik, Mahsa Shoaran. 1-2 [doi]
• A 24V-to-20V 6W 73.2%-Peak-Efficiency Isolated DC-DC Converter Using a Transformer-Based Supply-Generating TechniqueDongfang Pan, Weiwei Xu, Xiangfeng Wu, Aoyang Li, Lin Cheng 0001. 1-2 [doi]
• An Interference-Resilient 120-Degree-Apart Pseudo-I/Q BLE-Compliant Wake-Up Receiver Achieving -21dB SIR, -94dBm Sensitivity, and 4-D Wake-Up SignatureJunhong Sun, Changgui Yang, Yuxuan Luo 0001, Shurong Dong, Bo Zhao 0003. 1-2 [doi]
• A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOSJian Yang, Tailong Xu, Xi Meng, Zhenghao Li, Jun Yin 0001, Pui-In Mak, Rui Paulo Martins, Quan Pan 0002. 1-2 [doi]
• An 82dB-SNDR Input-Driving-Relaxed Noise-Shaping SAR with Amplifier-Reused In-Loop Buffering and NTF Leakage ReshapingTian Xie 0006, Ken Li, Tzu-Han Wang, Wei-En Lee, Engin Esen, Dong Suk Kang, Shaolan Li. 1-2 [doi]
• MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural NetworksXin Qiao, Jiahao Song, Youming Yang 0002, Renjie Wei, Xiyuan Tang, Meng Li 0004, Runsheng Wang, Yuan Wang 0001. 1-2 [doi]
• 2 Linearity and 104-Times Enhanced Retention TimeMinil Kang, Minseong Um, Jongun Won, Jaehyeon Kang, Sangjun Hong, Narae Han, Sangwook Kim, Sangbum Kim, Hyung-Min Lee. 1-2 [doi]
• An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOSYizhuo Wang, Hao Xu 0005, Guoyu Li, Shuai Liu, Yan Liu, Rui Yin, Hui Pan, Na Yan 0004. 1-2 [doi]
• Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and PackagingJihwan Kim, Ariel Cohen 0001, Mike Peng Li 0061, Ajay Balankutty, Sandipan Kundu, Ahmad Khairi, Yoel Krupnik, Yoav Segal, Marco Cusmai, Dror Lazar, Ari Gordon, Noam Familia, Kai Yu 0016, Yutao Liu, Matthew Beach, Priya Wali, Hsinho Wu, Masashi Shimanouchi, Jenny Xiaohong Jiang, Zhiguo Qian, Kemal Aygun, Itamar Levin, Frank O'Mahony. 1-8 [doi]
• A 10T2C Capacitive SRAM-based Computing-In-Memory Macro with Array-Embedded DAC and Shift-and-Add FunctionsEunhwan Kim, Hyunmyung Oh, Jehun Lee, JiHoon Park, Myeongeun Kwon, Jae-Joon Kim. 1-2 [doi]
• An Emulated Peak/Valley Curve Assisted Fast-Transient Buck Converter Achieving Precise One-Cycle Charge Balance with One-Parameter CalibrationZihao Tang, Mo Huang, Rui Paulo Martins, Yan Lu 0002. 1-2 [doi]
• A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTCPietro Salvi, Simone Mattia Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Andrea L. Lacaita, Salvatore Levantino. 1-2 [doi]
• A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOSChengyu Huang 0001, Kezhuo Ma, Sihao Chen, Jiaxuan Fan, Nan Sun 0001, Huazhong Yang, Xueqing Li. 1-2 [doi]
• A 92%-Efficiency 0.828μs Settling Time FC5L Voltage Regulator Featuring Time-Domain Charge Balancing & Flying Capacitor Self-Switching for Wide Dynamic Range & Fast Transient Chiplet ApplicationsXichen Sun, Jingshu Yu, Xuliang Wang, Jin Wei, Junmin Jiang, Chenchang Zhan, Yan Wang 0023, Xiaosen Liu. 1-2 [doi]
• 3DensityQiaobo Ma, Huihua Li, Jiahao Shi, Yang Jiang 0002, Rui Paulo Martins, Pui-In Mak. 1-2 [doi]
• A Closed-Loop EMI Regulated GaN Power Converter with 500MHz-Sampling-Bandwidth In-Situ EMI Sensing and 9kHz-Resolution Global Excess-Spectrum ModulationYingping Chen, Kaiwen Shen, Qing Yuan, Ming Liu. 1-2 [doi]
• A 32×32 Flash LiDAR SPAD Sensor with Up-to-1kfps Motional Target Detection by Threshold-adaptive 2D Dynamic VisionJingyi Wang, Zhangcheng Huang, Bu Chen, Hongyang Shang, Jiapei Zheng, Hankun Lv, Chixiao Chen, Qi Liu 0010, Ming Liu. 1-2 [doi]
• %-Peak-Efficiency Always-Dual-Path Buck-Boost Converter with Single-Mode Operation and Fast Transient ResponsesJi Jin, Yufa Zhou 0002, Weiwei Xu, Lin Cheng. 1-2 [doi]
• S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI ApplicationsMeng Wu, Wenjie Ren, Peiyu Chen, Wentao Zhao, Yiqi Jing, Jiayoon Ru, Zhixuan Wang, Yufei Ma 0002, Ru Huang 0001, Tianyu Jia, Le Ye. 1-2 [doi]
• Artificially Intelligent Closed-Loop Neurostimulators: Trade-Offs between Local and Remote ComputingJose De Sales Filho, Hossein Kassiri, Xilin Liu, Roman Genov. 1-7 [doi]
• A Mixed-Signal Near-Sensor Convolutional Imager SoC with Charge-Based 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest DetectionMartin Lefebvre 0002, David Bol. 1-2 [doi]
• 2per Channel Cryo-CMOS IC for 70-Channel Frequency-Multiplexed μs-Readout of Semiconductor QubitsQuentin Schmidt, Brian Martinez, Thomas Houriez, Baptiste Jadot, Aloysius G. M. Jansen, Xavier Jehl, Tristan Meunier, Gaël Pillonnet, Gérard Billiot, Adrien Morel, Yvain Thonnart, Franck Badets. 1-2 [doi]
• 2Sensor Size, 32.5μg/√Hz Noise Floor, High Efficiency MEMS Capacitive Accelerometer Using High-Voltage Pulse Excitation TechniqueLongjie Zhong, Pengpeng Shang, Shubin Liu 0001, Wenfei Cao, Lichen Feng, Yuhua Liang, Zhangming Zhu. 1-2 [doi]
• BioWAP: A Reconfigurable Biomedical AI Processor with Adaptive Processing for Co-Optimized Accuracy and Energy EfficiencyJian Liu, Zhuo-Yang Xie, Xiaoyang Wang, Xiang Liu, Xueguang Qiao, Jianchang Fan, Hongwei Qin, Cong Guo, Jianbiao Xiao, Shuisheng Lin, Jianhong Zhou. 1-8 [doi]
• A 38.5TOPS/W Point Cloud Neural Network Processor with Virtual Pillar and Quadtree-based Workload Management for Real-Time Outdoor BEV DetectionSukbin Lim, Jaehoon Heo, Jinho Yang, Joo-Young Kim 0001. 1-2 [doi]
• A 134-μW 50-MHz Quasi-Dynamic Comparator with A Novel Clock-Free Regenerative LatchSun-Yang Tay, Victor Adrian, Rouli Fang, Yanshan Xie, Joseph S. Chang. 1-2 [doi]
• A 20Gb/s QPSK Receiver with Mixed-Signal Carrier, Timing, and Data Recovery Using 3-bit ADCsShunichi Kubo, Yuji Gendai, Satoshi Miura, Shinsuke Hara, Satoru Tanoi, Akifumi Kasarnatsu, Takeshi Yoshida, Satoshi Tanaka, Shuhei Arnakawa, Minoru Fujishlrna. 1-2 [doi]