Table of Contents

• A Low-Power 1.2 TFLOPS/W Merge-Split RVV Processor for Mixed Scalar-Vector WorkloadsMattia Sinigaglia, Marco Bertuletti, Gianmarco Ottavi, Amirhossein Kiamarzi, Matteo Perotti, Giuseppe Tagliavini, Luca Benini, Davide Rossi 0001. 1-4 [doi]
• 2 RDC Using a Double-Settling RC Bridge and a Common-Mode Cancelling Series-Parallel Amplifier for Implantable Pressure and Strain MonitoringTim Keller, Arturo Di Girolamo, Yiyang Chen, Hesam Ghiasi, Donguk Seo, Yoonmyung Lee, Taekwang Jang. 1-4 [doi]
• 50-GBaud+ VCSEL-Based Co-Packaged Optical Links: An Overview of Circuits and SystemsSashank Krishnamurthy, Susnata Mondal, Junyi Qiu, Shuhei Yamada, Zhen Zhou, Joseph T. Kennedy, James E. Jaussi, Mozhgan Mansuri. 1-8 [doi]
• A 200kHz Self-powered Isolated Gate Driver for SiC and IGBT with Synchronous Regulation of 62.6% EfficiencyYang Liu, Yuan Yao, Guangqian Zhu, Dongfang Pan, Chenjie Hua, Xuliang Wang, Weiwei Xu, Yongyuan Li, Wing-Hung Ki, Lin Cheng, Zhangming Zhu. 1-4 [doi]
• A 56 Gb/s/wire, 0.75 pJ/b Transceiver for Die-to-Die Interface Using Simultaneous Bi-Directional SignalingSujay Patel, Mingyuan Han, Andrew Ng, Ruhao Xia, Mahmoud A. Khalil, Mohamed Badr Younis, Jack Kenney, Michael StGermain, Wei-Hung Chen, Pavan Kumar Hanumolu. 1-4 [doi]
• EinChip: A 4.6/1.5 TOPS/W 6/24b Log-compute Einsum-based Accelerator for Neuro Symbolic AILingyun Yao, Shirui Zhao, Marian Verhelst, Martin Andraud. 1-4 [doi]
• A Single-Channel 12GS/s 7b Time-Domain ADC Incorporating Self-Adaptive Time Amplifier Achieving >16.1GHz ERBW in 28nm CMOSHongzhi Liang, Peihe Liu, Pai Lin, Xuan Liu, Zhe Li, Yue Cao, Yixiao Luo, Li Dang, Haolin Han, Yi Shen 0007, Dengquan Li, Shubin Liu 0001, Ruixue Ding, Zhangming Zhu. 1-4 [doi]
• A 310μW Dynamic Ensemble Bayesian Filter Based ASIC with 94.2% Decoding Accuracy for Chinese Handwriting Trajectory ReconstructionJinyan He, Kangyu Su, Xinyun Zhu, Yu Qi, Yueming Wang 0001, Jian Xu. 1-4 [doi]
• A 45.9fs Cascaded Fractional-N DTC-Assisted Dual-Mode Harmonic-Mixing PLL with Adaptive Timing/Width Multi-Position InjectionLei Zhao, Xiaoxiong Zhang, Weimin Xue, Huanbiao Xu, Yiyang Shu, Xun Luo. 1-4 [doi]
• A SST-DAC Back-Gate Calibrated 5 GS/s CT Sigma Delta Modulator With 83 MHz BW, 100 dB SFDR and -95 dBc IM3 in 22 nm FD-SOIJulius Edler, Marcel Runge, Enne Wittenhagen, Chen-Chun Hsu, Frowin Buballa, Patrick J. Artz, Nikolaos Kioulos, Friedel Gerfers. 1-4 [doi]
• Aging- and Temperature-Resilient Chopper OPA with 19 nV/√Hz Noise and 2.6 μV Offset Using Continuous CM-Adaptive Background CalibrationMingqian Sun, Tianxiang Qu, Zhiliang Hong 0001, Jiawei Xu 0001. 1-4 [doi]
• Unicorn: A Unified Clock-and-Power SoC with RL-Adapted Digital SIMO Control and In-TRO Frequency Boosting for Edge ComputingXuliang Wang, Haoyu Wang, Xuchen Men, Renwei Chen, Junmin Jiang, Yan Wang, Xiaosen Liu. 1-4 [doi]
• A Single-Stage Synchronous Switch Regulating Rectifier with 93.3% End-to-End Efficiency and 15mV Output Ripple for Piezoelectric Energy HarvestingXiudeng Wang, Zhiming Chen, Libo Qian, Yang Liu, Yongyuan Li, Zhangming Zhu. 1-4 [doi]
• A 93% Peak Efficiency Buck Converter Enabling Operation with Variable Embroidered Yarn Inductance for Battery Powered In-textile SystemsAkiyoshi Tanaka, Zhenghong Chen, Jim Owens, Will Farrell, Daniel S. Truesdell, Benton H. Calhoun. 1-4 [doi]
• A 175-dB FoMS 12-bit 400-MS/s Pipeline-SAR ADC With an Optimized Detect-and-Skip Technique and a High-Efficiency Gain-Calibration-Free Amplification SchemeJiang Xu, Xuqiang Zheng, Zedong Wang, Hua Xu, Sai Li, Fangxu Lv, Mingche Lai, Xinyu Liu 0004. 1-4 [doi]
• A 184mW, 61fps Image Signal Processor for Spatial-Temporal HD Video InpaintingTai-Jung Chen, Yao-Kai Yang, Jun Nishimura, Chia-Hsiang Yang. 1-4 [doi]
• A Fully Integrated Gate-All-Around Ribbon FET Based Dual-Loop 1 GHz Switched-Capacitor Voltage Regulator with Anti-Leakage, Adaptive Dead Time and Self-Discharge FeaturesArvind Raghavan, Sivaraman Masilamani, Keng Chen, Huanhuan Zhang, Tamir Salus, Rachid Rayess. 1-4 [doi]
• PersASR: A 2.3-μJ/frame 96.8%-accurate TinyML Automatic Speech Recognition Processor with Data Augmentation-Driven Personalization in 16-nm FinFETSeungHyun Moon, Jinho Park, Chuan-Tung Lin, SeongHwan Cho, Gregory K. Chen, Phil C. Knag, Ram Krishnamurthy 0001, Mingoo Seok. 1-4 [doi]
• A Power DAC-Based Envelope-Tracking Supply Achieving 86.4% Efficiency and 400MHz Bandwidth for RF Power AmplifiersZhao Yang, Jiangfan Qi, Yu-an, Peng Cao, Peng Xu 0014, Jiawei Xu 0001, Zhiliang Hong 0001. 1-4 [doi]
• A Class-F23 Magnetic-Coupled 8-Phase Oscillator Employing Rotational Quadrifilar WindingChawin Khongprasongsiri, Sayan Kumar, Patchara Sawakewang, Robert Bogdan Staszewski, Teerachot Siriburanon. 1-4 [doi]
• A 256-Channel, 3.49-mW Wireless Neural Recording SoC with Adaptive Delta Compression and Error-Resilient CodingWenxian Gu, Liangjian Lyu, Zepeng Huang, Yingfei Xiang, Sirou Li, Wenjun Gong, Xing Wu 0005, C.-J. Richard Shi. 1-4 [doi]
• A 7.6-to-10.3GHz Mode-Switch-Less DM/CM Phase-Flipping Series-Resonance Oscillator Achieving 208.3dBc/Hz FoMTA at 10MHzHaokai Yang, Qiao Leng, Yiyang Shu, Xun Luo. 1-4 [doi]
• A 300MHz-BW Gm-C Filter Based Single-Loop CT-DSM Utilizing Pseudo Virtual Ground and Local Feedback Linearity-Enhanced Gm CellZhuojian Yao, Haikun Jia, Lilan Yu, Wei Deng 0001, Yu Fu, Junfeng Liu, Yue Liu, Baoyong Chi. 1-4 [doi]
• 3 Power DensityZhewen Yu, Junwei Huang, Zhiguo Tong, Zhongyao Zhu, Yan Lu 0002. 1-4 [doi]
• A 108.9dB-DR, 2-2 MASH ADC Featuring a Nested Gainboosting FIA with Gm Enhancement in Settling Phase Through Stepwise Charge SharingYuming Li, Lichenxi Zhang, Youxiang Chen, Kelei Zhang, Rui Pan, Junyao Ji, Jie Zhang, Xiaofei Wang, Hong Zhang. 1-4 [doi]
• A 40MHz Dual BEoL-RC Frequency Reference in 28nm CMOS with +440/-230ppm Inaccuracy from -55°C to 125°C and +940/+50ppm Inaccuracy After Accelerated AgingYihang Cheng 0003, Haiyu Wang, Ziyi Li, Minge Jiang, Xiaohan Liu, Yihan Zhang 0002, Huaqiang Wu, Sining Pan. 1-4 [doi]
• A 28nm 0.86μJ/Op Post-Quantum Secure Authentication Engine with 8.5fJ/bit TRNG and SCA/Fault Tolerance for Wireless Biomedical DevicesS. Jang, S. Maji, R. S. Agrawal, H. S. Lee, E. Lee, Giovanni Traverso, Anantha P. Chandrakasan. 1-4 [doi]
• A 500kHz 600V Capacitive Isolated SiC Converter with Switching-On Transition Detection for Hard-Switching Fault Prognosis Achieving 58ns Short-Circuit ProtectionQing Yuan, Yingping Chen, Ming Liu. 1-4 [doi]
• A 31.1 pJ/b Human Body Communication Transmitter with Standard-basis CDMA for Multi-Node IoB SystemsAnyu Jiang, Asif Iftekhar Omi, Ratul Kundu, Shreyas Sen, Baibhab Chatterjee. 1-4 [doi]
• A Reference-Less Inverter-Amplifier Based Programmable Laser Attack Sensor with 30mV SensitivityE. Berkowitz, Y. Atias, A. Baron, Yoav Weizman, Itamar Levi, Joseph Shor. 1-4 [doi]
• A 0.65V 13b 50MS/s Pipelined-SAR ADC with Cyclic Dynamic Amplifier and Bayesian-Based Gain CalibrationJiachang Yang, Haoyang Luo, Bingrui Li, Zichen Kong, Zongnan Wang, Jiarui Wang, Rongjia Bao, Haikang Diao, Xiyuan Tang. 1-4 [doi]
• A Timing-Skew-Free 12-bit 4-GS/s Pipelined TI-SAR ADC with a T/H-Based TI MDAC and a Combined Bit-Weight and Offset Background CalibrationYue Cao, Yi Shen 0007, Shubin Liu 0001, Le Chen, Lin Ling, Li Dang, Haolin Han, Hongzhi Liang, Dengquan Li, Zhangming Zhu. 1-4 [doi]
• A 26.4-to-56-Gb/s 0.38-pJ/bit PAM-4 Reference-less CDR Using Frequency-Offset Quantization Scheme Achieving 65-ns Constant-Band Acquisition Time in 28nm CMOSRunchen Wang, Yu Lv, Lingao Huang, Jiaxin Sun, Ya Zhao, Guohe Zhang, Li Geng, Chao Fan. 1-4 [doi]
• A Σ-Structure Ripple-Cancellation Switching Regulator with Automatic Ripple Calibration Achieving Sub-mV Output Voltage RippleHaoran Xu, Desheng Zhang 0003, Jingbin Wu, Chang Liu, Jianming Lei, Han Peng, Xuecheng Zou, Run Min, Qiaoling Tong. 1-4 [doi]
• A 400 × 400 Perovskite Image Sensor with Pixel-Wise Dynamic Self-Adjustment Using Time-Efficient Multiple Sampling and Adaptive ResolutionKyuik Cho, Sergey Tsarev, Quang Lung, Erfu Wu, Sergii Yakunin, Ivan Shorubalko, Maksym Kovalenko, Taekwang Jang. 1-4 [doi]
• 2 2.4mW 7-bit 3.5GS/s Single-Channel Time-Domain ADC with Folder, Time Amplifier, and Identical Coarse/Fine TDCs in 16nm FinFETMohammad Mahdi Ghahramani, Srujan Kumar Kaile, Gijin Park, Chiho Song, Yuanming Zhu, Il-Min Yi, Sebastian Hoyos, Samuel Palermo. 1-4 [doi]
• 3-SIMO: A 93.4% Quad-Level Quad-Mode Single-Inductor Quad-Output Buck-Boost Converter with Seamless Mode Transition and Single Clock Control for Flexible 1.8-9V InputsMun-Jung Cho, Seung-Ju Lee, Youngsin Jo, Yeon-Woo Jeong, Jong-Hun Kim, Min Sik Kim, Myeong-Ho Kim, Dong-chan Lee, Geon Kim, Min-Gyu Jeong, Se-un Shin. 1-4 [doi]
• An Ultra-Low-Power Capacitive Stacking Receiver Front-End with a PVT-Robust Switched-Capacitor-Based Feed-Forward IM3 Cancellation TechniqueJin Jin, Zhepu Xu, Bowei Xiao, Guisheng Yan, Danilo Manstretta, Wen Wu, Tongde Huang. 1-4 [doi]
• An 11bit, 140fs resolution, and 683fs INL Zero-Slope Digital-to-Time Converter for Fractional Frequency SynthesesKyeongwon Jeong, Hesam Omdeh Ghiasi, Seungki Hong, Sina Arjmandpour, Oscar Toomey, Taekwang Jang. 1-4 [doi]
• Multi-Spectral Filter-Less Computational Imager in Standard CMOS for Beyond-Visible Ubiquitous Machine Vision and Flexible Adaptation to ApplicationUdara Samurdhi Harshanga Kalingage, Karim Ali 0007, Ruiyuan Yang, Massimo Alioto. 1-4 [doi]
• MarginCiM: A 1.22 PetaOps/W, 2.5GS/s, 2.5pJ/correlation Margin-Processing Compute-in-Memory Array for RF to Feature ConversionKareem Rashed, Aswin Chowdary Undavalli, Shantanu Chakrabartty, Aravind Nagulu, Arun Natarajan 0001. 1-4 [doi]
• A 150-Msps 77-dB SNDR SAR ADC in 28-nm CMOSBingbing Yao, Jiangfan Wen, Likai Shen, Qide Cheng, Miao Meng, Hui Zhang, Lei Qiu 0002. 1-4 [doi]
• An 8.2μW Fully-Packaged Wireless Implantable SoC for Chemical and Electrical Neural Signal MonitoringMinghao Chen, Gangzhen Zhu, Wenjun Zhao, Hong Liao, Xiaoxu Yang, Yuqian Li, Jiahao Dong, Bingfang Wang, Zhiqiang Chang, Ying Fang, Jiangfeng Wu, Lei Qiu, Miao Meng. 1-4 [doi]
• A Comprehensive Power-Supply-Induced Jitter Mitigation Scheme for HBM Interfaces Using a Strobe-Triggered Digital LDO and Local Replica Regulators Achieving 10.7mV Voltage Droop and 1.4ns Settling TimeMyeongho Han, Jaeho Kim, Hyunjun Song, Jaehyouk Choi. 1-4 [doi]
• An Exponential-Decaying Current Gate Driver Achieving Ultra-Low Voltage Overshoot and 29.2% Cycle Loss Reduction for 1200V SiC MOSFETDesheng Zhang 0003, Haoran Xu, Jingbin Wu, Chang Liu, Jianming Lei, Han Peng, Xuecheng Zou, Run Min, Qiaoling Tong. 1-4 [doi]
• A 1.92um Pitch Current-Controlled Oscillator ADC Array Featuring Charge-Injection-Based Two-Stage Conversion for In-Memory ComputingDavid Iselin, Kyeongwon Jeong, Tim Keller, Giorgio Cristiano, Kwantae Kim, Woojun Choi, Oscar Toomey, Abhairaj Singh, Athanasios Vasilopoulos, Abu Sebastian, Manuel Le Gallo, Taekwang Jang. 1-4 [doi]
• A 3.6mW 5MS/s 100dB-SNDR 2-Step SAR ADC with Continuous-Time Second-Stage and Tracking AveragingCongyu Jin, Zhaoyang Shen, Xingshuai Zou, Xuanhao Zhang, Han Zhao, Zhong Zhang, Ning Ning, Hongshuai Zhang, Zheng Wang, Zhenbing Li, Shiheng Yang, Xiangyu Mao, Jiaxin Liu 0001. 1-4 [doi]
• A 0.6V 976nW 93.5dB-SNDR Charge-Pump ADC with 183.6dB-FoMs Using Passive-Reference Boost and NS-Assisted Charge-Balance-CalibrationShan Zhang, Lingxin Meng, Wanyuan Qu, Menglian Zhao, Zhichao Tan. 1-4 [doi]
• A Dynamic-Active Static-Sleep 18T Flip-Flop Supporting Retentive Clock Gating in 28nm CMOSDongkwon Lee, Donghyun Kim, Dongsuk Jeon. 1-4 [doi]
• A 230GHz, 128-unit Zero-IF Phased Array RX utilizing 1-D SSPLL and DTC Phase ShifterXiangao Meng, Yan Li, Jun Yuan, Zhiang Wang, Lihan Wang, Yinian Feng, Zheng Wang, Zhi Chen, Bo Zhang, Cheng Wang. 1-4 [doi]
• An 80.1dB-SNDR 1.5MHz-BW 3rd-Order Noise Shaping SAR ADC with Idle-free Residue ProcessingKun-Woo Park, Young-Hun Moon, Charlie Tahar, Hyeongjin Kim, Kwan-Hoon Song, Seung-Tak Ryu. 1-4 [doi]
• A Fully Integrated Constant-Current Switch-Capacitor Neuromodulator with 2.5D-Integrated Spike Sorting ASIC for Responsive NeurostimulationYouzhi Huang, Hao Jiang, Chixiao Chen, Yingping Chen, Qi Liu 0010, Ming Liu. 1-4 [doi]
• 68.22 TOPS/W Full Boolean Logic Supportable eDRAM-Based Digital CIM with Energy-Efficient Input-Aware Toggle-Rate-Reduced AdderIk-Hyeon Jeon, Ho Sung Lee, Eun-Bi Koh, Junsung Park, Joo-Hyung Chae. 1-4 [doi]
• Efficient and High-Speed Supply Modulation Techniques for 5G RF Power AmplifiersMinghao Shang, Changjin Chen, Chunyue Bo, Lin Cheng 0001. 1-8 [doi]
• An 8-GHz Stacked-Core VCO With Reliability Under Standard Supply and Explicit Second-Harmonic Tuning Achieving 193.4dBc/Hz FoM in 65-nm CMOSZhirui Zong, Renxu Yang. 1-4 [doi]
• A Crystal-Less Backscatter Tag Demonstrating Bi-Directional 802.11b-WiFi Communication with On-the-Fly Baseband ProcessingYongling Zhang, Lei Qiu, Patrick P. Mercier, Miao Meng. 1-4 [doi]
• A 10-bit 20-GS/s 4-Channel Time-Interleaved DAC Employing Hybrid-Segmentation in 28-nm CMOSYunjie Chen, Ckristian Duran, Koji Asami, Sota Kano, Ritaro Takenaka, Zolboo Byambadorj, Masahiro Ishida, Akio Higo, Tetsuya Iizuka. 1-4 [doi]
• A 6V-to-1V ReSC-Hybrid Two-Stage Merged Buck Converter with an Ultra-Small Inductor for VPDZhibang Song, Zhiguo Tong, Junwei Huang, Zhongyao Zhu, Sai-Weng Sin, Yan Lu 0002. 1-4 [doi]
• A 92.5 TOPS/W Fully-Analog Multi-Layer Computing-in-Memory for State-Space Models in 28nm CMOSLaith A. Shamieh, Wei-chun Wang, Narasimha Vasishta Kidambi, Saibal Mukhopadhyay. 1-4 [doi]
• A 433MHz Self-Regulated RF Energy Harvester with Absolute-Peak MPPT and ULP-Assisted Rectifier Core Achieving 91.5% PCE and 24.2dB PDRBerkay Özbek, Timothy G. Constandinou. 1-5 [doi]
• A 0.32-NEF, 0.08-PEF Discrete-Time Amplifier with Multi-Path kT/C Noise Cancellation in 180nm CMOSKe Hu, Jiangchao Wu, Xuanlin Chen, Zhao Wang, Hua Fan, Man Kay Law. 1-4 [doi]
• 2CIM: A 28nm 53.3 TFLOPS/W Decoding Digital CIM Macro for Efficient FlashMLA-based LLM InferenceJia Chen 0032, Zihao Xuan, Yewen Li, Zhuoya Yan, Zimu Li, Yat-Fong Yung, Yi Deng, Xiao Huo, Chi-Ying Tsui, Kwang-Ting Cheng, Fengbin Tu. 1-4 [doi]
• DualLearn: A 4.686pJ/SOP-4.026pJ/FLOP SNN-ANN Neuromorphic Inference-Training Processor with Distributed and Memory-Adaptive ArchitectureYi Zhong 0002, Zilin Wang 0001, Zhaoxiang Zhang 0001, Li Lun, Jinhao Ruan, Yipeng Gao, Yingying Cui, Xiaoxin Cui, Xing Zhang 0002, Yuan Wang 0001. 1-4 [doi]
• A 28nm 11.2-to-20-GHz PLL-based 16-Phase Clock Generator with High-Order-Mode Ring Oscillator Achieving 24.3-fs Jitter for 320-Gsps-Sample-Rate Data ConverterZonglin Ye, Longxiang Hou, Yuxuan Sun, Yuhan Ding, Yixuan Wen, Hongyang Zhang, Hao Luo, Yi Yang, Chenming Zhang, Xinlin Geng, Qian Xie 0002, Cheng Wang, Jun Zhou, Zheng Wang. 1-4 [doi]
• A 10MHz All-1.2V-NMOS Battery-Input Single-Mode Hybrid Buck-Boost Converter in 65nm CMOS with Fast Transient ResponseWenjie Yang, Zhiguo Tong, Zhewen Yu, Yan Lu 0002. 1-4 [doi]
• A 32-Gb/s 0.89-pJ/b Ground-Referenced PAM-4/NRZ Transceiver with Unidirectional Current Summation and Double SamplingWonbin Lee, Jae-Seung Jeong, Hyunmin Shin, In-Woo Jang, Namhoon Kim, Kyeongha Kwon. 1-4 [doi]
• THReaD: A 22.8 Mbps/node Two-dimensional Hierarchical Reconfigurable and Distributed Network for E-textiles with Fault Tolerance and Cooperative Power ManagementZhenghong Chen, Anjali Agrawal, Akiyoshi Tanaka, Trenton Elliott, Thomas Farrell, Zane Lewis, Will Farrell, Jim Owens, Daniel S. Truesdell, Benton H. Calhoun. 1-4 [doi]
• HDR-DTCP: High-Dynamic-Range Injectable Differential Tissue-Coupled Powering for Thread-Like Battery-Free Wireless StimulatorsAsif Iftekhar Omi, Anyu Jiang, Han Wu, Sultan Mahmud, Mali Halac, Shreyas Sen, Shriya Srinivasan, Adam Khalifa, Baibhab Chatterjee. 1-4 [doi]
• A 4D Radar Accelerator with Adaptive Sparse Processing for Real-Time Object DetectionSung-Eun Kim, Chang Eun Song, Byeonggon Kang, Maria Sojan, Omkar Sathe, Tajana Rosing, Mingu Kang. 1-4 [doi]
• A Fast-Transient Dual-Domain Learning Digital LDO with Droop Timing Prediction and Proactive Timing-Aware Control for Adaptive Droop MitigationMinkyu Song, Yunbeom Hwang, Taeho Lee, Jisu Kim, Jun-Eun Park. 1-4 [doi]
• A 1.16GHz -160.4dBFS/Hz-NSD multi-bit Continuous-Time Delta-Sigma ADC Achieving SNR/SNDR of 86dB/83dB in 17.5MHz-BW without DAC calibrationVaibhav Garg, Paras Garg, Ankur Bal, Sanyam Jain, Frédéric Paillardet, Kallol Chatterjee, Chandrajit Debnath, Gauri Mittal, Anand Kumar. 1-4 [doi]
• A 24V-to-1V Double Step-Down Converter Using Differentiated Inductor-Currents with Steady Common-Mode-Level Control for 1.5V/μs Line Transient ResponseRuichen Zhu, Hanshu Zhou, Yingping Chen, Ming Liu. 1-4 [doi]
• An 11.16μJ/token Edge SLM Decoder Accelerator with Scalable Ring-based Configuration for Token-level Pipelining in 16nm FinFETGuanchen Tao, Junyi Luo, Shiwei Liu 0002, Anhang Li, Gregory Kielian, Kauna Lei, Qirui Zhang 0001, Dennis Sylvester, Mehdi Saligane. 1-4 [doi]
• A Scalable Distributed 12-to-1V Fast-Slow Hybrid DC-DC Combo with Fast-Transient Bucklets and One-Pin Current BalancingJunwei Huang, Xiangyu Mao, Zhiguo Tong, Zhewen Yu, Shousheng Han, Rui Paulo Martins, Yan Lu 0002. 1-4 [doi]
• A 65nm CMOS-based Ingestible Capsule for Adaptable and pH-controlled Electrical Stimulation in GI-tractSaransh Sharma, Moaaz Fayumy, Leeban Morgan, Mehmet G. Say, Young-Geun Park, Jaehong Jung, Fan Xue, Mahmoud Elbeh, Sebastian Meier, Yogesh Ramadass, Zhansaya Makhambetova, Niora Fabian, Benedict Laidlaw, Khalil B. Ramadi, Joel Voldman, Giovanni Traverso, Anantha P. Chandrakasan. 1-4 [doi]
• A 28-nm Density-Capable 6ns Access Time MRAM Macro using Multi-bit Sense Amplifier and Dual-mode ECCJiongzhe Su, Haoran Du, Yantong Di, Bo Liu 0019, Hao Cai 0001. 1-4 [doi]
• A Sub-microwatt Blocker-Resilient Crystal-free Receiver for Ambient IoT ApplicationsAhmed Gharib Gadelkarim, Patrick P. Mercier. 1-4 [doi]
• A 0.2-to-22 GHz 24-Gbps Distributed Calibration-Free Full-band Interference-Rejection 64QAM/4096QAM Receiver with Integrated PLLs Achieving 83 dB Image-Rejection-Ratio and >61 dB Blocker RejectionDongze Li, Wei Deng 0001, Xiangyu Nie, Haikun Jia, Juntao Lan, Yichi Sun, Fuzhi Xue, Jinglin Zhang, Rui Wu 0001, Baoyong Chi. 1-4 [doi]
• A 0.38 ppm/°C High-Order Compensated Voltage Reference Using Digitized Temperature Range PartitioningXiaopeng Wang, Haiwen Tian, Huosheng Wen, Zhongxiao Tian, Jiaqi Yang, Lei Wang, Rui Bai 0001, Yifan Wu 0009, Shenglong Zhuo, Miao Meng, Lei Qiu 0002. 1-4 [doi]
• HyperV: A 130 HP-GFLOPS/W Out-of-Order RISC-V Vector Processor in 28 nm for Edge AIAndrew Ding, Eric Cheng, Eric Chan, Nader Bagherzadeh, Mohsen Imani. 1-4 [doi]
• One-Wire Architecture for Chiplet Reuse and Integration in Low-Dimensional SystemsAnil Kumar Gundu, Neelkamal Semwal, Massimo Alioto. 1-4 [doi]
• A Multi-Band IoT Tag Featuring a 150Mb/s Calibration-Free 64-QAM Backscatter Modulator and a 10Mb/s LO-Free DBPSK ReceiverYongling Zhang, Zheng Qin, Lei Qiu, Patrick P. Mercier, Miao Meng. 1-4 [doi]
• Toward Open-Source Chiplets for HPC and AI: Occamy and BeyondPaul Scheffler, Thomas Benz, Tim Fischer 0001, Lorenzo Leone, Sina Arjmandpour, Luca Benini. 1-8 [doi]
• A 25mW 2.2GS/s 12b Pipelined ADC with Polarity-Based Integrated MDAC and Gm-Ratio-Based Residue AmplifierHao Fang, Zhiyang Li, Xuehao Guo, Fuli Tian, Zhizhi Cai, ZhiYu Chen, Tingting Han, Chunyi Song, Zhiwei Xu 0003. 1-4 [doi]
• A 1.6-to-16 GHz Sub-1-LSB INLpp 7-bit Phase Interpolator Using Constant-Load Unit with Trimming-Free Digital Calibration in 28-nm CMOSXianting Su, Xiaoteng Zhao, Zekai Yang, Zhicheng Dong 0002, Miao Zhang, Jie Liu, HongYu Su, Bowen Wang 0001, Shubin Liu 0001, Zhangming Zhu. 1-4 [doi]
• A 28-nm CIM-Based Annealing Processor with One-Shot Weight Access, Dynamic Batching, and Bubble-Less Pipeline for Large-Scale Path Planning ProblemsBocheng Xu, Jinhao Ruan, Jiahao Song, Haikang Diao, Zihan Wu 0005, Haoyang Luo, Xiyuan Tang, Xiaochen Bo, Yuan Wang 0001. 1-4 [doi]
• A Simultaneous 16-Channel Adiabatic Charge-Tracking Stimulator with 87.4% Stimulator Efficiency and Low Load SensitivityEojin Kim, Janghwan Kim, Jaeseong Park, Seongjae Moon, Geunchang Seong, Su Yeon Jeon, Seonae Jang, Young-Sang Cho, Sohmyung Ha, Chul Kim. 1-4 [doi]
• A 120A 48-60V to 0.8-1V Full Bridge Converter with Hybrid Current Doubler Rectifier Achieving 6.9% Heavy-Load Efficiency EnhancementZhiren Luo, Zeguo Liu, Yichao Ji, Ji Jin, Zikang Wang, Weiyi Tang, Hao Wang, Mo Huang, Lin Cheng 0001. 1-4 [doi]
• Circuit Architectures for Next-Generation Neural Interfaces: Recording, Stimulation, and Closed-Loop NeuromodulationXiaolin Yang, Qiuyang Lin, Yoontae Jung, Aitor Rivero-Cortazar, Chutham Sawigun, Bogdan C. Raducanu, Jose Cisneros-Fernández, Joan Aymerich, Carolina Mora Lopez. 1-8 [doi]
• An Analog-to-Cipher Converter, ACCHaruki Okada, Takuji Miki, Ryozo Takahashi, Makoto Nagata, Jun Shiomi, Yoshihiro Midoh, Rei Ueno, Noriyuki Miura. 1-4 [doi]
• A 256 Gb/s 5.4 Vppd non-Distributed Stacked Driver with Dual Current Injection Swing Boosting Technique for TFLN Optical Modulators in 65nm CMOSZiyi Lin, Haikun Jia, Wei Deng 0001, Ziyue Dang, Peiqi Zhou, Zihan Zhou, Daigao Chen, Zhihua Wang 0001, Xi Xiao, Baoyong Chi. 1-4 [doi]
• An 85.1dB-SNDR 1MHz-BW Noise-Shaping SAR ADC with kT/C Noise-Shaping and 96fF Sampling CapacitorByeongjin Son, Jongyoon Won, Kyungmin Kang, Yong Lim, Youngcheol Chae. 1-4 [doi]
• A 99.5dB-SNR Self-Timed Highly-Flexible Capacitance-to-Digital Converter With Fast Zoom TechniqueZhidi Yang, Menglian Zhao, Zhichao Tan. 1-4 [doi]
• 2 BF16×1-bit CIM-based BERT Accelerator in 28nm CMOSQijia Xie, Weiran Chen, Qilong Chen, Dingbang Liu, Ziyi Guan, Kai Li, Haoxiang Peng, Jingyun Gu, Changwen Chen, Ngai Wong 0001, Mingqiang Huang, Hao Yu 0001. 1-4 [doi]
• First Demonstration of an NVSRAM-Based PUF with Ultra-Low BER through Minimal Redundancy ECCJ. Zhang, Y. Liang, M. Zhao, X. Li, K. Liu, Y. Su, N. Li, H. Sun, Y. Zhang, X. Ma, K. Wang, S. Ding, P. Yao, S. Pan, J. Tang, B. Gao, D. Wu, Z. Zhang, L. Chen, H. Qian, L. Pan, H. Wu. 1-4 [doi]
• 2 External-Clock-Less Phase-to-Voltage Converter Based on Phase Compression and Linearizing Offset Achieving 1.05%-FSR LinearityHongkun Li, Yiyang Shu, Xun Luo. 1-4 [doi]
• A 28nm 34mW Zero Knowledge Proof Processor with Reconfigurable Modular Multiplier Array and Memory-based Successive Excess ReductionSangouk Jeon, Sungjin Park, BeomSeok Kim, JuYoung Oh, Dongsuk Jeon. 1-4 [doi]
• A 105.8-dB DR Continuous-Time Delta-Sigma Modulator with SH-free Quantizer and PVT-adaptive Negative-RYuming Li, Youxiang Chen, Junyao Ji, Rui Pan, Zhiming Li, Ruitao Wang, Jie Zhang, Hong Zhang. 1-4 [doi]
• A Fully Integrated SPAD Sensor with Photoluminescent Encapsulation and Die-Bonded μLEDs for Implantable Oxygen MonitoringJulian A. Singer, Anton Geläschus, Ute Schmidt, Andreas Bahr, Matthias Kuhl, Qiang Li. 1-4 [doi]
• A 0.5V 13.7pJ/pulse 802.15.4/4z UWB Tag and Coherent Quadrature-Hybrid-Correlation Receiver Chipset for Passive Localization SystemsLonghao Kuang, Yunzhao Nie, Woogeun Rhee, Wei Deng 0001, Zhihua Wang 0001. 1-4 [doi]
• A Buck-Based SIBO Converter with 5mV Load-Independent Vop Ripple and Enhanced Von Ripple Suppression for AMOLED DisplayZihao Tang, Jiacheng Yang, Rui Paulo Martins, Lin Cheng 0001, Mo Huang. 1-4 [doi]
• Fully Integrated CSCR-based Single-Stage Piezoelectric Energy Harvesting Interface with Independent Positive-/Negative-Cycle MPPTGuangshu Zhao, Chenxi Wang, Ningchao Lin, Hao Wu, Litao Zhang, Haoyang Sang, Man Kay Law. 1-4 [doi]
• 2 Temperature-Robust 7.2GHz Fractional-N RO-PLL Achieving 257.9fsrms Jitter and -255.5dB FoMNHaoran Li, Jinge Li, Shangmin Yu, Xiaoqi Lin, Xueying Jiang, Xi Meng, Pui-In Mak, Rui Paulo Martins, Jun Yin 0001. 1-4 [doi]
• A RF Sub-Sampling ADC with Hierarchical Sharing Interleaver Achieving >34.5/41dB SNDR/SFDR for Up to 40GHz Ka-Band InputsZijian Liu, Minglei Zhang, Yannan Zhang, Zehang Wu, Yan Zhu 0001, Rui Paulo Martins, Chi-Hang Chan. 1-4 [doi]
• Automated Design of a 22-41-GHz Phased Array TRX Front-End with Adaptive Analog Temperature Compensation for Multi-Band 5G CommunicationsRuitao Wang, Zhongxu Tian, Jieying Huang, Hong Zhang, Yan Wang. 1-4 [doi]
• A 5nm 91.43 TOPS/W 4-Chiplet Generalizable-Rendering-Processor with UCIe-Enabled Cross-Die-Cache and Balance-Aware Progressive Multi-Level SparsityYonghao Tan, Songchen Ma, Pingcheng Dong, Peng Luo, Zhiyuan Lei, Wencai Lu, Guangxi Ying, Manto Yung, Hai Zhao 0001, Lan Liu, Yuzhong Jiao, Xuejiao Liu, Yu Liu, Li Li, Luhong Liang, Mao Liu, Kwang-Ting Cheng. 1-4 [doi]
• A Fully Integrated 0.25Vpp-to-44Vpp 249 Level THD+N=0.3% Ultrasonic MEMS-Driver with a Power Reduction Factor of 22Moritz Gruber, Björn Eversmann, Lei Liao, Ralf Brederlow. 1-4 [doi]
• STELLA: A 16nm Spatio-Temporal Elastic Low-Latency CGRA for Multi-Stage Pipelined ApplicationsJun Yin 0001, Chao Fang 0005, Ryan Antonio, Xiaoling Yi, Yunhao Deng, Fanchen Kong, Marian Verhelst. 1-4 [doi]
• A 29-40 GHz 6-Bit Phase Filtering Active Phase Shifter with <1.8°/<0.38 dB RMS Phase/Gain Errors for 5G Millimeter-Wave Spatial-Filtering ReceiversTao Zhang 0086, Xinyuan Nie, Jiaxun Lv, Haohui Chen, Xiaoxian Liu, Qijun Lu, Bei Liu, Xin An, Lisheng Chen, Zhangming Zhu. 1-4 [doi]
• A 14GHz 16-Phase Calibration-Free Fractional-N Ring-PLL with 118fs Jitter Using Phase- and Voltage-domain Quantization Error CancellationMahmoud A. Khalil, Mohamed Badr Younis, Mohamed Osama Selim, Mohamed Saad Aly, Ruhao Xia, Ahmed E. AbdelRahman, Yongxin Li 0001, Pavan Kumar Hanumolu. 1-4 [doi]
• An H-Band CMOS Frequency Doubler with 6.01dBm Single-Element Pout and 1.49%-DC-to-RF-Efficiency Using Dual-Harmonic Continuous-Mode Tuning TechniqueWeiping Wu, Yanjun Ma, Xun Bao, Lei Zhang, Aoyang Zhang. 1-4 [doi]
• A 100-Gb/s Burst-Mode Optical Receiver With 9-Tap Pipelined FFE and Amplitude/Phase Adaptation in 28-nm CMOSPingyi Cai, Ruixian Zhang, Xiongshi Luo, Kun Zhang, Wenhan Guan, Jiayao Li, Wenkang Luo, Yangyi Zhang, Chenyang Wang, Quan Pan 0002. 1-4 [doi]
• nd Harmonics Co-Circulation Quad-Core Inverse Class-F Oscillator Achieving 199.1dBc/Hz Peak FoM in 65nm CMOSJunnan Guan, Hanzhang Cao, Jin Jin, Wen Wu 0005, Tongde Huang. 1-4 [doi]
• A 64-Gb/s QPSK Carrier-Phase-Recovery Loop with Wide IF Range Using Dual-Oscillator Frequency TranslationMohamed Osama Selim, Mohamed Saad Aly, Mahmoud A. Khalil, Mohamed Badr Younis, Mostafa Gamal Ahmed, Ahmed E. AbdelRahman, Sujay Patel, Karim Elmeligy, John Burns, Pavan Kumar Hanumolu. 1-4 [doi]
• A 28.71ppm/°C Voltage Reference with 0.00002% Line Sensitivity and 35μs Startup Time for High Voltage ApplicationsYining Wang, Xing Li, Yan Lu. 1-4 [doi]
• DOIM140: A 140-spin, all-to-all connected, Oscillator Ising Machine IC in 180nm CMOSA. Gagan Deep Goru, Shreesha Sreedhara, C. Venkata Pavan Sumanth Sikhakollu, Thomas Jagielski, Rajit Manohar, Jaijeet S. Roychowdhury. 1-4 [doi]
• Ultra-Compact 0.6-108 GHz Nonuniform Distributed Amplifier Using Parasitic-Canceling Cascode Gain Cell and Signal-Reused Coupled-Transmission-Lines in 28-nm Bulk CMOSQiqi Luo, Jie Zhou 0026, Xun Luo. 1-4 [doi]
• 3-Volume Inductor for Flicker-Free Mobile OLED DisplaysSueon Park, Jun-Gi Lee, Jae-Hyun Kim, Dong-Kyu Kim, Sung-Chun Park, Yongjae Lee, Hyun-Sik Kim. 1-4 [doi]
• A 16nm 0.67pJ/bit 80Mb/s Circuit-System Co-Optimized Time Domain Brain Channel ReceiverHarshit Naman, Gourab Barik, Sarthak Antal, Samyadip Sarkar, Ming-Che Li, Shreyas Sen. 1-4 [doi]
• Fractional-N PLL-Based Micro-Oven Control for Ultra-Stable MEMS Frequency ReferencesKarim Elmeligy, Rakibul Islam, Jintark Kim, Mohamed Badr Younis, Jie Yan, Jiawei Yang, Gabrielle D. Vukasin, Hyun-Keun Kwon, Thomas W. Kenny, Gaurav Bahl, Pavan Kumar Hanumolu. 1-4 [doi]
• A 64.5 TFLOPS/W 16-nm AI Training Accelerator with 4T-eDRAM for Efficient Gradient and Activation HandlingNestor Cuevas, Thierry Tambe, Sai Qian Zhang, David Brooks 0001, Gu-Yeon Wei. 1-4 [doi]
• A 25GS/s Single Track and Hold with 65GHz Bandwidth Featuring 38.8dB SNDR and 50.6dBc SFDR at 50.7GHz Input in 22nm CMOSMarcel Runge, Daniel Lobitz, Ols Hidri, Ingo Dettmann, Thorsten Siera, Friedel Gerfers. 1-4 [doi]
• A 36-Channel ToF-PET Chip Based on Multi-Threshold Trigger with 10.4 ps Resolution, 49-bit Dynamic Range, 900 kcps Throughput and 52.9 ps Intrinsic-Channel JitterYouze Xin, Han Wang, Pengfei Hu, Yiyun Xie, Hongxu Chen, Xuhu Wang, Chi Wang, Congzhen Hu, Bing Zhang 0019, Li Geng. 1-4 [doi]
• A 256 GHz 8×8 2-D Beamforming Transceiver in 40 nm CMOSSatoshi Tanaka, Kyoya Takano, Shinsuke Hara, Y. Miyoshi, L. Xu, Koki Mochida, Z. Yan, S. Beppu, Hideki Yagi, T. Noguchi, Yoshiki Sugimoto, Kunio Sakakibara, Tatsuo Hagino, Satoru Tanoi, Mohamed H. Mubarak, Akifumi Kasamatsu, Shunichi Kubo, Takeshi Yoshida 0001, Shuhei Amakawa, Minoru Fujishima. 1-4 [doi]
• A 32Gb/s/lane 0.83Tb/s/mm UCIe Compliant Die-to-Die Link Over 25mm Standard PackageZhaokai Liu, Susnata Mondal, Yuanming Zhu, Sashank Krishnamurthy, Shuhei Yamada, Junyi Qiu, Soumya Bose, Zuoguo Wu, Gerald Pasdast, James E. Jaussi, Mozhgan Mansuri. 1-4 [doi]
• A 4.75GHz Digital PLL Achieving 30.4fs jitter under 5mVpp Supply Ripples Using a Voltage-Biased Oscillator with Adaptive Supply Sensitivity Cancellation and Common-Mode Resonance TuningStefano Gallucci, Daniele Lodi Rizzini, Riccardo Moleri, Michele Rossoni, Pietro Salvi, Damiano Fagotti, Francesco Tesolin, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino. 1-4 [doi]
• 2 Ternary/INT/FP LLM Accelerator with Lossless Weight CompressionMengtian Yang, Yipeng Wang 0017, Chieh-Pu Lo, Xiuhao Zhang, Tzuping Huang, Sirish Oruganti, Jaydeep P. Kulkarni. 1-4 [doi]
• 3 Power DensityKai Yuan, Junmin Jiang, Chenzhou Ding, Ka Nang Leung, Xun Liu 0002. 1-4 [doi]
• A 0.65V 10-to-21.5GHz Time-amplifying-based Sampling PLL Achieving 41.3-67.3fs jitter and -255dB Peak FoMTDepeng Sun, Yan Zhu 0001, Dingtao Zeng, Yuan Gao 0011, Feng Bu, Bowen Wang 0001, Hao Xu 0005, Na Yan 0004, Ruixue Ding, Shubin Liu 0001, Zhangming Zhu. 1-4 [doi]
• A Reconfigurable Monolithic Microwave Photonic FIR Filter in 45nm CMOS SOIHenry Love, Firooz Aflatouni. 1-4 [doi]
• Soft-Output Threshold-Guided CRC Decoding with SOGRAND in 40nm CMOSZeynep Ece Kizilates, Arslan Riaz, Akshaya Bali, Jiewei Feng, Muriel Médard, Ken R. Duffy, Rabia Tugce Yazicigil. 1-4 [doi]
• A 14b 1GS/s Single-Channel Pipelined-SAR ADC with a 4-bit/cycle Sub-Quantizer and a Reconfigurable Miller Ring AmplifierGuo Wei, Rui Zhang, Peng Wang, Fule Li, Hanjun Jiang, Zhihua Wang 0001. 1-4 [doi]
• A Hybrid Piezo-Fan and Thermoelectric CPU cooling System Achieving Coefficient of Performance of 7.2 and 117% EfficiencySi-Yu Liao, Yu-Jia Wei, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 1-4 [doi]
• TOKCIM: A 65nm All-Digital Compute-in-Memory Transformer Accelerator with Advanced Weight Sparsity Handling and SoftMax AccelerationShaoxuan Li, Zikun Wei, Ruihao He, Cong Wang, Ye Gu, Tianchu Dong, Yucheng Cai, Hongwu Jiang. 1-4 [doi]
• A 28 GHz Ultra-Compact Two-Stage Doherty Power Amplifier with a Three-Transformer FootprintKun Gao, Shuyang Li, Shun Wan, Shunhua Hu, Yudi Yang, Zixuan Wang, Zan Zhou, Wenhua Chen 0002. 1-4 [doi]
• 2, 4 TB/s bandwidth 3D Logic-on-SRAM Stacking CGRA ChipZizheng Dong, Chen Yin, Pengyu Liu, Shuaipeng Li, Ang Li 0045, Weijia Zhu, Weifeng He, Guanghui He 0002, Qin Wang 0009, Yanan Sun 0003, Zhigang Mao, Naifeng Jing, Jianfei Jiang 0001. 1-5 [doi]
• A 22nm 15.2μJ/Inference Speech Enhancement Accelerator with Contextual-Aware KV-Cache Management and Reconfigurable D-CIM EngineQinzhe Zhi, Wenjie Ren, Siyuan He, Mingxuan Li, YanDong He, Le Ye, Tianyu Jia. 1-4 [doi]
• A 94.1% Peak Efficiency Coupled-Inductor Boost Converter with Small Inductor Current Ripple and Fast Transient ResponseShousheng Han, Junwei Huang, Fei Song, Zhiguo Tong, Sai-Weng Sin, Hanjun Jiang, Xiaoming Wu, Tianling Ren, Yan Lu 0002. 1-4 [doi]
• A DTC-Based Digital PLL Achieving -64.5dBc Fractional Spur and 80fs Jitter with a 2-Track Probability-Density-Shaping ΔΣ Modulator and a Dithered-Threshold TDCRiccardo Moleri, Daniele Lodi Rizzini, Michele Rossoni, Damiano Fagotti, Pietro Salvi, Stefano Gallucci, Andrea Leonardo Lacaita, Salvatore Levantino, Simone Mattia Dartizio. 1-4 [doi]
• AI-enabled RFICKaushik Sengupta, Jonathan Zhou, Emir Ali Karahan, Juho Park, Muhamed Allam, Sherif Ghozzy. 1-8 [doi]
• An 83-F2 2T PUF Featuring Isolated Hot-Carrier Injection and Lightweight Majority-Voting-Based Strong PUF ModeZhenzhe Chen, Kunyang Liu, Weirong Dong, Quan Cheng, Jiamin Li, Longyang Lin, Takashi Sato 0001. 1-4 [doi]
• A 4x4 MIMO Equalizer for Polarization Crosstalk Cancellation in 160 Gb/s DP-QPSK/16QAM Coherent Optical ReceiversMohamed Saad Aly, Mohamed Osama Selim, Mostafa Gamal Ahmed, Ruhao Xia, Ahmed Hegazi, Sujay Sanjiv Patel, Mohamed Badr Younis, Mahmoud A. Khalil, Ahmed E. AbdelRahman, John Burns, Pavan Kumar Hanumolu. 1-4 [doi]
• A 0.36μJ/Classification Intra- and Inter-Individually Insensitive PCG Monitoring SoC with Dynamic Framing and Reconfigurable Computing ArrayYuheng Wang, Hongzhi Zhao, Yuanzhe Zhao, Yan Zhu 0001, Rui Paulo Martins, Chi-Hang Chan, Minglei Zhang. 1-4 [doi]
• A 13-b 320-MS/s Noise-Successive-Attenuated SAR ADC with R-C-Traded-Off Reference BufferJiangfan Wen, Qide Cheng, Shenglong Zhuo, Miao Meng, Hui Zhang, Bingbing Yao, Lei Qiu 0002. 1-4 [doi]
• A 28-nm Optical Flow Estimation Accelerator with Redundancy Speculation, Bit-Width-Aware Compression and Similarity DetectionTao Zhang 0140, Yi Zhong 0002, Youming Yang 0002, Jinhao Ruan, Yipeng Gao, Zhaoxiang Zhang 0001, Yuan Wang 0001. 1-4 [doi]
• An Energy-Efficient 197-to-210GHz 4×4 Beam-Steerable Radiator Array with Integrated Microbump Radiation and 1.35% DC-to-RF Efficiency in 65-nm CMOSHuibo Wu, Xuan Liu, Xingcun Li, Yuqun Liu, Liang Gao, Yue Li, Wenhua Chen. 1-4 [doi]
• A 12-25GHz Ring-PLL Clock Generator Achieving 98fs Jitter and <-52dBc Spurs Using a 22fs Quadrupler and Sub-Sampling Error ExtractionMohamed Badr Younis, Mahmoud A. Khalil, Mohamed Osama Selim, Mohamed Saad Aly, Ruhao Xia, Ahmed E. AbdelRahman, Yongxin Li 0001, Emad Hegazi, Pavan Kumar Hanumolu. 1-4 [doi]
• A 63.9-aF 17.6-bit Adaptive-Load and Configurable Zoom Capacitance-to-Digital Converter with 43.3-pF RangeQingjiang Xia, Fei Zhou, Yuze Niu, Zhaofeng Huang, Mingzhong He, Xuefei Du, Wengao Lu, Yacong Zhang, Zhongjian Chen. 1-4 [doi]
• A 26-Channel Fully-Integrated SoC with Autonomous In-Situ Reconfiguration for Trapped-Ion Shuttling in 130nm BCDAlexander Meyer, Marius Neumann, Zhaoqun Guo, Paul Julius Ritter, M. Badawy, M. Hartmann, Mohammad Abu Zahra, M. Ebner, H. Thabet, S. Fischer, Michael Sieberer, Jens Repp, Meinhard Schilling, Benedikt Hampel, Matthias Brandl, Vadim Issakov. 1-4 [doi]
• 2 Resolution FoM in 28nm CMOSShangjie Wei, Huanfa Sun, Yucong Li, Puxi Tan, Yi Xiong, Yu Su, Chenyao Cao, Yukun He, Xiaoyan Gui. 1-4 [doi]
• A 0.71-pJ/bit 64-Gb/s PAM-4 CDR Using a Charge-Calculated-Linear Phase Detector Achieving 12MHz JTOL@1UI and 361fs Recovered Clock in 28nm CMOSRunchen Wang, Lingao Huang, Yu Lv, Ya Zhao, Guohe Zhang, Li Geng, Pui-In Mak, Chao Fan. 1-4 [doi]
• ROM-LTE: A 28nm 16.1TOPS/W ROM-Based LUT Tensor Engine with Complementary ROM and Switching-Suppressed Latch-Based PE for Fine-Tuning-Free ML InferenceSangsu Jeong, Jeongkyu Park, Dongsuk Jeon. 1-4 [doi]
• A 157-Gb/s/mm 1.55-pJ/bit Correlated PAM4 Transceiver with Immunity to Crosstalk, Simultaneous Switching and Common-Mode Noise for High-Density Interconnect in 28nm CMOSGeng Zhang 0001, Fangxu Lv, Mingche Lai, Liquan Xiao, Ruixiao Kuai, Liangyong Yuan, Chao Fan, Lizhou Wu, Guohe Zhang. 1-4 [doi]
• 2, 2Vpp-Input-Range, 95dB-SNDR, 178.5dB-FOMs Noise-Shaping SAR ADC for Closed-Loop Neural InterfacesYiheng Fu, Cong Huang, Alin Thomas Tharakan, Fei Tan, Jieun Joo, Jiahuai Fan, Raphael Berner, Kyojin Choo, Mahsa Shoaran. 1-4 [doi]
• A 7.6-ppm/°C Frequency Reference From -40 ℃ to 125 ℃ with Series-Parallel Double-Tracking for Second-Order Compensation and Process-Variation ToleranceWenzhao Lv, Dan Ye, Pengxu Ren, Kai Xu, Mingyang Qin, Zhonghua Wang, Chao Jiang, Zhuojun Chen. 1-4 [doi]
• A 16nm 2.2pJ/b High Efficiency Pulse-Position Modulated Resonance Transceiver for 15Mbps Multi-Source High-Speed Body-Area Sensor NetworkAnhang Li, Ruichen Qi, Yuhao Yuan, Juan Moya, Dennis Sylvester, Mehdi Saligane. 1-4 [doi]
• A Pulse-Width-Modulated Temporal Interference Stimulator IC with Local and Global Charge Balancing for Selective Peripheral Nerve StimulationQuynh-Trang Nguyen, Kim-Hoang Nguyen, Duy Minh Nguyen, Xuan Khanh Nguyen, Loan Pham-Nguyen, Minkyu Je. 1-4 [doi]
• A Feedback-Free Slope-to-Voltage Ratio MPPT Decoupled from TON Generator for Thermoelectric Energy Harvesting with 2.5mV-750mV Input RangeXiudeng Wang, Jiakai Chen, Zhiwen Hou, Libo Qian, Qiujin Chen, Yang Liu, Yongyuan Li, Zhangming Zhu. 1-4 [doi]
• An Output Power Extendable 5-to-8V-Input 0.8-to-1.2V-Output SC-Parallel CSCR Converter with 20mV Undershoot For Vertical Power DeliveryYongjuan Shi, Chen Hu, Quan Pan, Xun Liu 0002, Junmin Jiang. 1-4 [doi]
• A 30kHz-BW 100.6dB-SNDR ΔΣ Modulator with Swapped Sampling-Feedback Operation and Optimized kT/C Noise CancellationXuanhao Zhang, Han Zhao, Congyu Jin, Hongshuai Zhang, Zheng Wang, Zhong Zhang, Ning Ning, Zhenbing Li, Xiangyu Mao, Shiheng Yang, Jiaxin Liu 0001. 1-4 [doi]
• Over-the-Air Frequency Calibration for Crystal-Less BLE Nodes Achieving ±20 ppm Accuracy at -23 dB SIRAmir Arsalan Kiavar, Niels Fakkel, Masoud Babaie. 1-4 [doi]
• A 28nm Secure Processor for Transformer-based Generative AI with On-Chip Authentication and Model Protection for Mobile DevicesShiyu Guo, Jie Gu. 1-4 [doi]
• 2/Ch Spatiotemporal Spike Feature ExtractorHaoyang Luo, Zongnan Wang, Jingjun Zhu, Zihan Wu 0005, Jiarui Wang, Rongjia Bao, Changxuan Dong, Xianya Feng, Youming Yang, Bingrui Li, Haikang Diao, Hongji Sun, Xiaojie Duan, Yuan Wang 0001, Xiyuan Tang. 1-4 [doi]
• A 262dB DC-gain 47.5MHz-Bandwidth 2.68nV/√Hz - Noise Dual-Chopper Operational AmplifierYarallah Koolivand, Seyed Alireza Mosavian, Danial Khabbazipour, Yasser Rezaeiyan, Alireza Mosalmani, Reza Shokri, Mohammad Mehdi Beheshti, Milad Zamani, Farshad Moradi. 1-4 [doi]
• A 22nm Continual Learning Accelerator for Autonomous Systems with 69.2TOPS/W Dynamic-Sparse-Weight-Updat and Dual-Mode Vector-Scaled-INT4 ProcessingJunnosuke Suzuki, Takuma Ishibashi, Hikari Otsuka, Yasuyuki Okoshi, Kota Ando, Daichi Fujiki, Masato Motomura. 1-4 [doi]
• A 10GHz Double-Edge Sampling PLL with 12.8fsrms Jitter and -257.8dB FoMJ in 65nm CMOS ProcessFeng Bu, Depeng Sun, Ge Wang, Zonglin Li, Zhou Shu, Bowen Wang 0001, Hao Xu 0005, Na Yan 0004, Ruixue Ding, Shubin Liu 0001, Zhangming Zhu. 1-4 [doi]
• 3 Power Density for AI ComputingYongjuan Shi, Xun Liu 0002, Chen Hu, Tiantian Tang, Ping Wang, Quan Pan, Junmin Jiang. 1-4 [doi]
• A Class-G Current-Steering Power Amplifier with Digital Linearization Supporting 160 MHz 1024-QAM in 40 nm CMOS Achieving -39.9 dB EVM and 28.9% PAETanwei Yan, Zhiyong Zhang, Junning Jiang, Scott L. Miller, Jose Silva-Martinez. 1-4 [doi]
• A Dual-Band Flat-Gain Power Amplifier with 19.3 dBm P1dB and 33.5% PAE1dB Empowered by the Novel Dual-Band Coupler for 64-/256/- QAM 5G NR SignalsPingyang Huang, Jilong Yang, Li Zhang 0137, Shengfu Zhao, Shizeng Zhang, Xiaofang Gao, Xiang Yi, Zhiyuan Cheng, Qiang Cui. 1-4 [doi]
• A Reconfigurable LP/BP/HP Current-Sensing Front-End Achieving 109.3-dB SFDR and Tolerance to Error Current and Sensor Parasitics with Adaptive Auto-Zeroing Scheme Embedded in SC-CMFBYun-Hung Gao, Chun-Ho Fan, Junwen Li, Yuan-Ting Zhang, Ka Nang Leung, Kong-Pang Pun. 1-4 [doi]