Abstract is missing.
- Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy MinimizationKimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda. 1-3 [doi]
- A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable ComputersJunichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai. 1-3 [doi]
- A 0.4-0.9V, 2.87pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan Markus Hiienkari, Navneet Gupta, Jukka Teittinen, Jesse Simonsson, Matthew J. Turnquist, Jonas Eriksson, Risto Anttila, Ohto Myllynen, Hannu Rämäkkö, Sofia Mäkikyrö, Lauri Koskinen. 1-3 [doi]
- XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCsDionysios Diamantopoulos, Florian Scheidegger, Stefan Mach, Fabian Schuiki, Germain Haugou, Michael Schaffner, Frank K. Gürkaynak, Christoph Hagleitner, A. Cristiano I. Malossi, Luca Benini. 1-3 [doi]
- An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly DetectionTakuya Sakuma, Hiroki Matsutani. 1-3 [doi]
- MMT-based Multi-channel Video Transmission System with Synchronous Processing ArchitectureYasuhiro Mochida, Takahiro Yamaguchi, Ken Nakamura. 1-3 [doi]
- A Novel In-DRAM Accelerator Architecture for Binary Neural NetworkHaerang Choi, Yosep Lee, Jae-Joon Kim, Sungjoo Yoo. 1-3 [doi]
- User Insensible Sliding Firmware Update Technique for Flash-Area/Time-Cost Reduction toward Low-Power Embedded Software ReplacementJisu Kwon, Moon Gi Seok, Daejin Park. 1-3 [doi]
- Tileable Monolithic ReRAM Memory DesignMeenatchi Jagasivamani, Candace Walden, Devesh Singh, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce Jacob, Donald Yeung. 1-3 [doi]
- A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAMDennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Heiner Bauer, Farkas Csaszar, Robert Niebsch, Jörg Schreiter, Holger Eisenreich, Sebastian Höppner. 1-3 [doi]
- Energy-efficient Design of an STT-RAM-based Hybrid Cache ArchitectureMasayuki Sato 0001, Xue Hao, Kazuhiko Komatsu, Hiroaki Kobayashi. 1-3 [doi]
- Space Responsive Multithreaded Processor (SRMTP) for Spacecraft ControlShota Nakabeppu, Yosuke Ide, Masahiko Takahashi, Yuta Tsukahara, Hiromi Suzuki, Haruki Shishido, Nobuyuki Yamasaki. 1-3 [doi]