Abstract is missing.
- Power Analysis of Directly-connected FPGA ClustersKensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano. 1-6 [doi]
- DXT501: An SDR-Based Baseband MP-SoC for Multi-Protocol Industrial Wireless CommunicationYang Chen, Lin Liu, Xuelin Feng, Jinglin Shi. 1-6 [doi]
- An Efficient Reference Image Sharing Method for the Parallel Video Encoding ArchitectureKen Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato 0001, Hiroe Iwasaki, Hiroaki Kobayashi. 1-3 [doi]
- A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML ApplicationsMoritz Scherer, Alfio Di Mauro, Georg Rutishauser, Tim Fischer, Luca Benini. 1-3 [doi]
- Encoder-based Many-Pattern Matching on FPGAsHoang Gia Vu, Ngoc-Dai Bui. 1-5 [doi]
- Hardware Acceleration of Aggregate Signature Generation and Authentication by BLS Signature over BLS12-381 curveKaoru Masada, Ryohei Nakayama, Makoto Ikeda. 1-3 [doi]
- Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent OperationsYuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi. 1-6 [doi]
- A Low-power and Real-time 3D Object Recognition Processor with Dense RGB-D Data Acquisition in Mobile PlatformsDongseok Im, Gwangtae Park, Junha Ryu, Zhiyong Li, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Wonhoon Park, Hankyul Kwon, Hoi-Jun Yoo. 1-3 [doi]
- A Memcapacitive Spiking Neural Network with Circuit Nonlinearity-aware TrainingReon Oshio, Sugahara Takuya, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima. 1-6 [doi]
- Reinforcement Learning based Efficient Mapping of DNN Models onto AcceleratorsShine Parekkadan Sunny, Satyajit Das. 1-6 [doi]
- Body Bias Control on a CGRA based on Convex OptimizationTakuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano. 1-3 [doi]
- Ultra-low Latency 8K Video-transmission System Utilizing Disaggregation ConfigurationYasuhiro Mochida, Daisuke Shirai, Koichi Takasugi. 1-3 [doi]