Table of Contents

• COSMOS: A Compiled Simulator for MOS CircuitsRandal E. Bryant, Derek L. Beatty, Karl S. Brace, K. Cho, Thomas J. Sheffler. 9-16 [doi]
• A Fast Signature Simulation Tool for Built-In Self-Testing CircuitsS. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter. 17-25 [doi]
• An Improved Systematic Method for Constructing Systolic Arrays from AlgorithmsNikrouz Faroughi, Michael A. Shanblatt. 26-34 [doi]
• Predicting Area-Time Tradeoffs for Pipelined DesignRajiv Jain, Alice C. Parker, Nohbyung Park. 35-41 [doi]
• A Prototype Framework for Knowledge-Based Analog Circuit SynthesisRamesh Harjani, Rob A. Rutenbar, L. Richard Carley. 42-49 [doi]
• Standard Cell Placement Using Simulated SinteringLov K. Grover. 56-59 [doi]
• ESP: A New Standard Cell Placement Package Using Simulated EvolutionRalph-Michael Kling, Prithviraj Banerjee. 60-66 [doi]
• The Making of VIVID: A Software Engineering PerspectiveJonathan B. Rosenberg. 74-81 [doi]
• Architecture and Design of the MARS Hardware AcceleratorPrathima Agrawal, William J. Dally, Ahmed K. Ezzat, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar. 101-107 [doi]
• Circuit Simulation on the Connection MachineDonald M. Webber, Alberto L. Sangiovanni-Vincentelli. 108-113 [doi]
• Aesop: A Tool for Automated Transistor SizingKye S. Hedlund. 114-120 [doi]
• Delay Optimization of Combinational Static CMOS LogicM. Hofmann, J. K. Kim. 125-132 [doi]
• Geometrical Compaction in One Dimension for Channel RoutingJ. Royle, Mikael Palczewski, H. VerHeyen, N. Naccache, Jiri Soukup. 140-145 [doi]
• Routing L-Shaped Channels in Nonslicing-Structure PlacementH. H. Chen. 152-158 [doi]
• Via Minimization for Gridless LayoutsNicholas J. Naclerio, Sumio Masuda, Kazuo Nakajima. 159-165 [doi]
• An Overview of Logic Synthesis SystemsLouise Trevillyan. 166-172 [doi]
• Realistic Fault Modeling for VLSI TestingWojciech Maly. 173-180 [doi]
• Demand Driven Simulation: BACKSIMSteven P. Smith, M. Ray Mercer, B. Brodk. 181-187 [doi]
• Faster Architectural Simulation Through ParallelismJ. W. Smith, K. S. Smith, Robert J. Smith II. 189-194 [doi]
• Force-Directed Scheduling in Automatic Data Path SynthesisPierre G. Paulin, John P. Knight. 195-202 [doi]
• Knowledge Based Control in Micro-Architecture DesignForrest Brewer, Daniel Gajski. 203-209 [doi]
• REAL: a program for REgister ALlocationFadi J. Kurdahi, Alice C. Parker. 210-215 [doi]
• Abstract Routing of Logic Networks for Custom Module GenerationSteven T. Healey, William J. Kubitz. 230-236 [doi]
• Accelerated Transition Fault SimulationMichael H. Schultz, Franc Brglez. 237-243 [doi]
• On Accuracy of Switch-Level Modeling of Bridging Faults in Complex GatesRochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana. 244-250 [doi]
• Functional Verification of MOS CircuitsDaniel Weise. 265-270 [doi]
• On the Verification of Sequential Machines at Differing Levels of AbstractionSrinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton. 271-276 [doi]
• Application of Term Rewriting Techniques to Hardware Design VerificationMandalagiri S. Chandrasekhar, J. P. Privitera, K. W. Conradt. 277-282 [doi]
• Logic Verification Algorithms and Their Parallel ImplementationHi-Keung Tony Ma, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli, R. Wei. 283-290 [doi]
• Generating Incremental VLSI Compaction Spacing ConstraintsC. W. Carpenter, Mark Horowitz. 291-297 [doi]
• Nutcracker: An Efficient and Intelligent Channel SpacerXiao-Ming Xiong, Ernest S. Kuh. 298-304 [doi]
• Improving Virtual-Grid Compaction Through GroupingLars S. Nyland, Stephen W. Daniel, D. Rogers. 305-310 [doi]
• KAHLUA: A Hierarchical Circuit DisassemblerBill Lin, A. Richard Newton. 311-317 [doi]
• Benchmarks for Cell-Based Layout SystemsBryan Preas. 319-320 [doi]
• VALKYRIE: A Validation Subsystem of a Version Server for Computer-Aided Design DataRajiv Bhateja, Randy H. Katz. 321-327 [doi]
• Querying Part Hierarchies: A Knowledge-Based ApproachArnon Rosenthal, Sandra Heiler. 328-334 [doi]
• An Object-Oriented Approach to Data Management: Why Design Databases Need ItSandra Heiler, Umeshwar Dayal, Jack A. Orenstein, S. Radke-Sproull. 335-340 [doi]
• DAGON: Technology Binding and Local Optimization by DAG MatchingKurt Keutzer. 341-347 [doi]
• Mesh Arrays and LOGICIAN: A Tool for Their Efficient GenerationJ. A. Beekman, Robert Michael Owens, Mary Jane Irwin. 357-362 [doi]
• Finding the Optimal Variable Ordering for Binary Decision DiagramsSteven J. Friedman, Kenneth J. Supowit. 358-356 [doi]
• Strip Layout: A New Layout Methodology for Standard Circuit ModulesJ. Apte, Gershon Kedem. 363-369 [doi]
• The ALGIC Silicon Compiler System: Implementation, Design Experience and ResultsJohannes Schuck, Norbert Wehn, Manfred Glesner, G. Kamp. 370-375 [doi]
• A Dynamic and Efficient Representation of Building-Block LayoutWayne Wei-Ming Dai, Masao Sato, Ernest S. Kuh. 376-384 [doi]
• BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic ArraysChun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya. 385-391 [doi]
• On Computing Optimized Input Probabilities for Random TestsHans-Joachim Wunderlich. 392-398 [doi]
• VLSI Circuit Testing Using an Adaptive Optimization ModelPhilip S. Yu, C. Mani Krishna, Yann-Hang Lee. 399-406 [doi]
• Circular Self-Test Path: A Low-Cost BIST TechniqueAndrzej Krasniewski, Slawomir Pilarski. 407-415 [doi]
• PHRAN-SPAN: A Natural Language Interface for System SpecificationsJohn J. Granacki Jr., Alice C. Parker. 416-422 [doi]
• TED: A Graphical Technology Description EditorW. Lee, G. Liu, K. Peterson. 423-428 [doi]
• ? : A Context-Sensitive Help System Based on HypertextW. Lee. 429-435 [doi]
• VISION: VHDL Induced Schematic Imaging on Net-ListsR. K. Chun, K.-J. Chang, Lawrence P. McNamee. 436-442 [doi]
• Fast, Small, and Static Combinatorial CMOS CircuitsBertrand Serlet. 451-458 [doi]
• LCS - A Leaf Cell Synthesizer Employing Formal Deduction TechniquesP. A. Subrahmanyam. 459-465 [doi]
• An Interface between VHDL and EDIFM. Shahdad. 472-478 [doi]
• Where VHDL Fits Within the CAD EnvironmentJ. Hines. 491-494 [doi]
• A Hierarchical Approach Test Vector GenerationSusheel J. Chandra, Janak H. Patel. 495-501 [doi]
• A Topological Search Algorithm for ATPGTom E. Kirkland, M. Ray Mercer. 502-508 [doi]
• Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara CircuitsM. Ladjadj, J. F. McDonald. 509-515 [doi]
• An Overview of the Penn State Design SystemRobert Michael Owens, Mary Jane Irwin. 516-522 [doi]
• TRIP: An Automated Technology Mapping SystemShigenobu Suzuki, Tatsushige Bitoh, Masao Kakimoto, Kazutoshi Takahashi, Takao Sugimoto. 523-529 [doi]
• Array Optimization for VLSI SynthesisD. F. Wong, C. L. Liu. 537-543 [doi]
• Layout Optimization of CMOS Functional CellsR. L. Maiasz, John P. Hayes. 544-551 [doi]
• The Design Automation Standards EnvironmentRonald Waxman. 559-561 [doi]
• Design Automation Standards Need IntegrationL. O Connell. 562-562 [doi]
• HPEX: A Hierarchical Parasitic Circuit ExtractorShun-Lin Su, Vasant B. Rao, Timothy N. Trick. 566-569 [doi]
• RED: Resistance Extraction for Digital SimulationDon Stark, Mark Horowitz. 570-573 [doi]
• Function Search from Behavioral Description of a Digital SystemJung-Gen Wu, William P.-C. Ho, Yu Hen Hu, David Y. Y. Yun, H. J. Yu. 574-579 [doi]
• Boolean Comparison by SimulationEdward P. Stabler, H. Bingol. 584-587 [doi]
• Statistics for Parallelism and Abstraction Level in Digital SimulationLarry Soulé, R. Blank. 588-591 [doi]
• A Conceptual Framework for Designing ASIC HardwareSteven S. Leung, Michael A. Shanblatt. 592-595 [doi]
• CASE: An Integrated Design Environment for Algorithm-Driven ArchitecturesDick C. A. Bulterman. 596-599 [doi]
• Improving a PLA Area by Pull-Up Transistor FoldingChidchanok Lursinsap, Daniel Gajski. 608-614 [doi]
• On Yield Consideration for the Design of Redundant Programmable Logic ArraysChin-Long Wey. 622-628 [doi]
• Routing with a Scanning Window-8Ma Unified ApproachD. Kaplan. 629-632 [doi]
• General Purpose RouterRichard J. Enbody, H. C. Du. 637-640 [doi]
• A Path Selection Global RouterY. C. Hsu, Y. Pan, William J. Kubitz. 641-644 [doi]
• A New Compaction Scheme Based on Compression RidgesP. C. Shah, Hosaker N. Mahabala. 645-648 [doi]
• Hierarchical Design Based on a Calculus of NetsBernd Becker, Günter Hotz, Reiner Kolla, Paul Molitor, Hans-Georg Osthof. 649-653 [doi]
• An Application of Exploratory Data Analysis Techniques to Floorplan DesignE. F. M. Kouka, Gabriele Saucier. 654-658 [doi]
• LES: A Layout Expert SystemY.-L. S. Lin, Daniel Gajski. 672-678 [doi]
• Design and Algorithms for Parallel Testing of Random Access and Content Addressable MemoriesPinaki Mazumder, Janak H. Patel, W. Kent Fuchs. 689-694 [doi]
• A Dynamic Programming Approach to the Test Point Insertion ProblemBalakrishnan Krishnamurthy. 695-705 [doi]
• Fast Printed Circuit Board RoutingJeremy Dion. 727-734 [doi]
• EASE: A Design Support Environment for the HDDL ELLAJ. D. Morison, N. E. Peeling, T. L. Thorp, E. V. Whiting. 741-749 [doi]
• CHESHIRE: An Object-Oriented Integration of VLSI CAD ToolsL.-P. Demers, P. Jacques, S. Fauvel, Eduard Cerny. 750-756 [doi]
• STEM: An IC Design Environment Based on the Smalltalk Model-View-Controller ConstructEmil F. Girczyc, Tai A. Ly. 757-763 [doi]
• Rational for and Organization of the Engineering Information System ProgramAnthony J. Gadient, J. L. Ebel. 764-769 [doi]
• A Discrete Heuristics Approach to Predictive Evaluation of Semi-Custom IC LayoutsAli A. Minai, Ronald D. Williams, F. W. Blake. 770-776 [doi]
• A Rule-Based Placement System for Printed Wiring BoardsGotaro Odawara, T. Hamuro, Kazuhiko Iijima, T. Yoshino, Y. Dai. 777-785 [doi]
• A Rule-Based Circuit Representation for Automated CMOS Design and VerificationChing-Farn Eric Wu, Anthony S. Wojcik, Lionel M. Ni. 786-792 [doi]
• A High Performance Routing EngineT. D. Spiers, D. A. Edwards. 793-799 [doi]
• A Hardware Accelerator for Maze RoutingYoungju Won, Sartaj Sahni, Yacoub M. El-Ziq. 800-806 [doi]
• Performance of a Parallel Algorithm for Standard Cell Placement on the Intel HypercubeM. Jones, Prithviraj Banerjee. 807-813 [doi]
• A Preliminary Investigation into Parallel Routing on a Hypercube ComputerKunle Olukotun, Trevor N. Mudge. 814-820 [doi]
• Functional Abstraction from Structure in VLSI Simulation ModelsRichard H. Lathrop, Robert J. Hall, Robert S. Kirk. 822-828 [doi]