Abstract is missing.
- A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow GraphsM. Potkonjack, Jan M. Rabaey. 7-12 [doi]
- Efficient Sparse Matrix Factorization for Circuit Simulation on Vector SupercomputersP. Sadayappan, V. Visvanathan. 13-18 [doi]
- A Framework for Scheduling Multi-Rate Circuit SimulationA. P.-C. Ng, V. Visvanathan. 19-24 [doi]
- Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit SimulatorPatrick Odent, Luc J. M. Claesen, Hugo De Man. 25-30 [doi]
- Gate Matrix Layout Synthesis with Two-Dimensional FoldingIchiang Lin, David Hung-Chang Du, Steve H.-C. Yen. 37-42 [doi]
- Transistor Size Optimization in the Tailor Layout SystemDavid Marple. 43-48 [doi]
- VLSI Design Language Standardization Effort in JapanOsamu Karatsu. 50-55 [doi]
- Experience with ADAM Synthesis SystemRajiv Jain, Kayhan Küçükçakar, Mitch J. Mlinar, Alice C. Parker. 56-61 [doi]
- Architectural Partitioning for System Level DesignElizabeth D. Lagnese, Donald E. Thomas. 62-67 [doi]
- Integrated Scheduling and Binding: A Synthesis Approach for Design Space ExplorationM. Balakrishnan, Peter Marwedel. 68-74 [doi]
- Scheduling High-Level Blocks for Functional SimulationZhicheng Wang, Peter M. Maurer. 87-90 [doi]
- Massively Parallel Switch-Level Simulation: A Feasibility StudySaul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar. 91-97 [doi]
- Data Parallel Simulation Using Time-Warp on the Connection MachineM. J. Chung, Y. Chung. 98-103 [doi]
- LASSIE: Structure to Layout for Behavioral Synthesis ToolsM. T. Trick, Stephen W. Director. 104-109 [doi]
- Performance optimized floor planning by graph planarizationB. Lokanathan, Edwin Kinnen. 116-121 [doi]
- ORCA a Sea-of-Gates Place and Route SystemMitsuru Igusa, Mark Beardslee, Alberto L. Sangiovanni-Vincentelli. 122-127 [doi]
- The Social Implications of Computerization: Making the Technology HumaneMichael C. McFarland. 129-134 [doi]
- GABRIEL: A Design Environment for Programmable DSPsEdward A. Lee, E. Goei, H. Heine, W. Ho, S. Bhattacharyya, Jeffery C. Bier, E. Guntvedt. 141-146 [doi]
- Automatic Synthesis of Microprogrammed Control Units from Behavioral DescriptionsA. Kumar, S. Kumar, P. Kulshreshtha, S. Ghose. 147-154 [doi]
- A New Approach to the Rectilinear Steiner Tree ProblemJan-Ming Ho, Gopalakrishnan Vijayan, C. K. Wong. 161-166 [doi]
- A New Heuristic for Single Row Routing ProblemsNaveed A. Sherwani, Jitender S. Deogun. 167-172 [doi]
- IRSIM: An Incremental MOS Switch-Level SimulatorA. Salz, Mark Horowitz. 173-178 [doi]
- Automatic Generation of Behavioral Models from Switch-Level DescriptionsDavid Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh. 179-184 [doi]
- CASE Environments for Design AutomationAnthony I. Wasserman. 193-196 [doi]
- An Object Oriented Approach to CAD Tool Control within a Design FrameworkJames Daniell, Stephen W. Director. 197-202 [doi]
- DeBuMA: Description, Building and Management of ApplicationsClaudia S. Frydman, Norbert Giambiasi, M. Gatumel, P. Bayle. 203-208 [doi]
- Multi-Level Logic Synthesis Using Communication ComplexityTingTing Hwang, Robert Michael Owens, Mary Jane Irwin. 215-220 [doi]
- Efficient Prime Factorization of Logic ExpressionsPatrick C. McGeer, Robert K. Brayton. 221-225 [doi]
- New Methods in the Analysis of Logic Minimization Data and AlgorithmsAlan J. Coppola. 226-231 [doi]
- The Layout Synthesizer: An Automatic Netlist-to-Layout SystemC. C. Chen, S.-L. Chow. 232-238 [doi]
- GENAC: An Automatic Cell Synthesis ToolChong-Leong Ong, Jeong-Tyng Li, Chi-Yuan Lo. 239-244 [doi]
- A Module Generator for Optimized CMOS BuffersAsim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili. 245-250 [doi]
- Use of Change Coordination in an Information-rich Design EnvironmentMarianne Winslett, David W. Knapp, K. Hall, Gio Wiederhold. 252-257 [doi]
- Protection and Versioning for OCTMário J. Silva, David Gedye, Randy H. Katz, R. Newton. 264-269 [doi]
- Approaches to Multi-level Sequential Logic SynthesisSrinivas Devadas. 270-276 [doi]
- Multi-level Logic Simplification Using Don t Cares and FiltersAlexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 277-282 [doi]
- Automatic Synthesis of Boolean Equations Using Programmable Array LogicRajeev Goré, Kotagiri Ramamohanarao. 283-289 [doi]
- An Efficient Two-Dimensional Layout Compaction AlgorithmH. Shin, Chi-Yuan Lo. 290-295 [doi]
- Technology Tracking of Non Manhattan VLSI LayoutJ. Waterkamp, R. Wicke, R. Brück, M. Reinhardt, G. Schrammeck. 296-301 [doi]
- Automatic Tub Region Generation for Symbolic Layout CompactionChi-Yuan Lo. 302-306 [doi]
- Three Competing Design Methodologies for ASIC s: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module GenerationKurt Keutzer. 308-313 [doi]
- General Decomposition of Sequential Machines: Relationships to State AssignmentSrinivas Devadas. 314-320 [doi]
- State Assignment Using a New Embedding Method Based on an Intersecting Cube TheoryGabriele Saucier, Christopher Duff, Franck Poirot. 321-326 [doi]
- NOVA: State Assignment of Finite State Machines for Optimal Two-level Logic ImplementationsTiziano Villa, Alberto L. Sangiovanni-Vincentelli. 327-332 [doi]
- A Parallel Branch and Bound Algorithm for Test GenerationSrinivas Patil, Prithviraj Banerjee. 339-343 [doi]
- Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational CircuitsHyung Ki Lee, Dong Sam Ha, K. Kim. 345-350 [doi]
- A Deterministic Approach to Adjacency Testing for Delay FaultsC. Thomas Glover, M. Ray Mercer. 351-356 [doi]
- Parallel Pattern Fault Simulation of Path Delay FaultsMichael H. Schulz, Franz Fink, Karl Fuchs. 357-363 [doi]
- Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial PlacementSomchai Prasitjutrakul, William J. Kubitz. 364-369 [doi]
- Performance-driven Placement of Cell Based IC sMichael A. B. Jackson, Ernest S. Kuh. 370-375 [doi]
- An Analytic Optimization Technique for Placement of Macro-CellsAlexander Herrigel, Wolfgang Fichtner. 376-381 [doi]
- An Investigation into Statistical Properties of Partitioning and Floorplanning ProblemsSarma Sastry, Jen-I Pi. 382-387 [doi]
- Multi Chip ModulesR. H. Bruce, W. P. Meuli, J. Ho. 389-393 [doi]
- Automatic Layout of Silicon-on-Silicon Hybrid PackagesBryan Preas, Massoud Pedram, D. Curry. 394-399 [doi]
- A Neural Network Design for Circuit PartitioningJih-Shyr Yih, Pinaki Mazumder. 406-411 [doi]
- A Study of the Applicability of Hopfield Decision Neural Nets to VLSI CADM. L. Yu. 412-417 [doi]
- Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault SimulationK. Cho, Randal E. Bryant. 418-423 [doi]
- Differential Fault Simulation - a Fast Method Using Minimal MemoryWu-Tung Cheng, Meng-Lin Yu. 424-428 [doi]
- VVDS: A Verification/Diagnosis System for VHDLHeh-Tyan Liaw, K.-T. Tran, Chen-Shang Lin. 435-440 [doi]
- Verification of Hardware Descriptions by Retargetable Code GenerationLothar Nowak, Peter Marwedel. 441-447 [doi]
- GRASP: A Grammar-based Schematic ParserCyrus Bamji, Jonathan Allen. 448-453 [doi]
- Design for Manufacturability and YieldAndrzej J. Strojwas. 454-459 [doi]
- FACE Core Environment: The Model and Its Application in CAE/CAD Tool DevelopmentWilliam D. Smith, David A. Duff, M. Dragomirecky, J. Caldwell, Michael J. Hartman, Jeffrey R. Jasica, Manuel A. d Abreu. 466-471 [doi]
- An Approach to Intelligent Assistance for the Specification of ASIC Design Using Objects and RulesKlaus D. Müller-Glaser, J. Bortolazzi. 472-477 [doi]
- Representation and Use of Design Rules within a Technology Adaptable CAD SystemJúlio S. Aude, Hilary J. Kahn. 478-484 [doi]
- Computing Signal Delay in General RC Networks by Tree/Link PartitioningPak K. Chan, Kevin Karplus. 485-490 [doi]
- Worst-case Delay Estimation of Transistor GroupsSerge Gaiotti, Michel Dagenais, Nicholas C. Rumin. 491-495 [doi]
- An O(nlogm) Algorithm for VLSI Design Rule CheckingCharles R. Bonapace, Chi-Yuan Lo. 503-507 [doi]
- Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic BehaviourIvo Bolsens, W. De Rammelaere, Luc J. M. Claesen, Hugo De Man. 513-518 [doi]
- A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive TestingWen-Ben Jone, Christos A. Papachristou. 525-534 [doi]
- A Scheme for Overlaying Concurrent Testing of VLSI CircuitsWen-Ben Jone, Christos A. Papachristou, M. Pereira. 531-536 [doi]
- ELF: A Tool for Automatic Synthesis of Custom Physical CAD SoftwareDorothy E. Setliff, Rob A. Rutenbar. 543-548 [doi]
- High-Level Graphical User Interface Management in the FACE Synthesis EnvironmentM. Dragomirecky, Ephraim P. Glinert, Jeffrey R. Jasica, David A. Duff, William D. Smith, Manuel A. d Abreu. 549-554 [doi]
- On the General False Path Problem in Timing AnalysisDavid Hung-Chang Du, S. H. Yen, Subbarao Ghanta. 555-560 [doi]
- Efficient Algorithms for Computing the Longest Viable Path in a Combinational NetworkPatrick C. McGeer, Robert K. Brayton. 561-567 [doi]
- Static Timing Analysis of Dynamically Sensitizable PathsS. Perremans, Luc J. M. Claesen, Hugo De Man. 568-573 [doi]
- Average Interconnection Length and Interconnection Distribution Based on Rent s RuleCarol V. Gura, Jacob A. Abraham. 574-577 [doi]
- Efficient Final Placement Based on Nets-as-PointsXueqing Zhang, Lawrence T. Pillage, Ronald A. Rohrer. 578-581 [doi]
- PIAF: A Knowledge-based/Algorithm Top-Down Floorplanning SystemMarwan A. Jabri, David J. Skellern. 582-585 [doi]
- Efficient Floorplan Area OptimizationD. F. Wong, P. S. Sakhamuri. 586-589 [doi]
- A Parallel Row-based Algorithm for Standard Cell Placement with Integrated Error ControlJeff S. Sargent, Prithviraj Banerjee. 590-593 [doi]
- A Note on Clustering Modules for FloorplanningJohn D. Gabbe, P. A. Subrahmanyam. 594-597 [doi]
- An Interactive Tool for Register-level Structure OptimizationDavid Knapp. 598-601 [doi]
- A Technology-adaptive Allocation of Functional Units and ConnectionsNam Sung Woo, H. Shin. 602-605 [doi]
- VHDL Synthesis Using Structured ModelingJoseph Lis, Daniel Gajski. 606-609 [doi]
- Evaluation of a Reconfigurable Architecture for Digital Beamforming Using the OODRA WorkbenchDavid L. Hwang, Thomas L. Wernimont, W. Kent Fuchs. 614-617 [doi]
- FACET: A CAE System for RF Analogue Simulation Including LayoutR. F. Milsom, K. J. Scott, S. G. Clark, J. C. McEntegart, S. Ahmed, F. N. Soper. 622-625 [doi]
- A Novel Algorithm for Improving Convergence Behavior of Circuit SimulatorsZhiping Yu, Weijian Zhao, Zhilian Yang, Y. Edmund Lien. 626-629 [doi]
- iSMILE: A Novel Circuit Simulation Program with Emphasis on New Device Model DevelopmentAndrew T. Yang, S. M. Kang. 630-633 [doi]
- A Novel Approach to Accurate Timing Verification Using RTL DescriptionsKaushik Roy, Jacob A. Abraham. 638-641 [doi]
- Algorithms for Accuracy Enhancement in a Hardware Logic SimulatorPrathima Agrawal, R. Tutundjian, William J. Dally. 645-648 [doi]
- Efficient Algorithms for Extracting the K most Critical Paths in Timing AnalysisS. H. Yen, David Hung-Chang Du, Subbarao Ghanta. 649-654 [doi]
- Timing Analysis in a Logic Synthesis EnvironmentN. Weiner, Alberto L. Sangiovanni-Vincentelli. 655-661 [doi]
- Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing SimulatorJacques Benkoski, Andrzej J. Strojwas. 668-673 [doi]
- Special Purpose Architecture for Accelerating Bitmap DRCNarasimha B. Bhat, S. K. Nandy. 674-677 [doi]
- An Efficient Finite Element Method for Submicron IC Capacitance ExtractionN. P. van der Meijs, Arjan J. van Genderen. 678-681 [doi]
- Resistance Extraction and Resistance Calculation in GOALIE?Kuang-Wei Chiang. 682-685 [doi]
- From Network to ArtworkL. Stok, G. P. Koster. 686-689 [doi]
- REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular StructuresI. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man. 694-697 [doi]
- A Comparison of Four Two-dimensional Gate Matrix Layout ToolsMary Jane Irwin, Robert Michael Owens. 698-701 [doi]
- Plowing: Modifying Cells and Routing 45: 9D - LayoutsKnut M. Just, Werner L. Schiele, Th. Krüger. 702-705 [doi]
- On the Repair of Redundant RAMsV. G. Hemmady, Sudhakar M. Reddy. 710-713 [doi]
- CMOS Stuck-open Fault Detection Using Single Test PatternsRochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya. 714-717 [doi]
- ATLAS/ELA: Scan-based Software Tools for Reducing System Debug Time in a State-of-the-art WorkstationBulent I. Dervisoglu, M. A. Keil. 718-721 [doi]
- A Functional-Level Test Generation Methodology Using Two-level RepresentationsU. J. Davé, Janak H. Patel. 722-725 [doi]
- A New Approach to Derive Robust Sets for Stuck-open Faults in CMOS Combinational Logic CircuitsJ. F. Wang, T. Y. Kuo, J. Y. Lee. 726-729 [doi]
- A Simplified Six-waveform Type Method for Delay Fault TestingWeiwei Mao, Michael D. Ciletti. 730-733 [doi]
- A Massively Parallel Algorithm for Fault Simulation on the Connection MachineVinod Narayanan, Vijay Pitchumani. 734-737 [doi]
- A New Model for the High Level Description and Simulation of VLSI NetworksA. J. van der Hoeven, A. A. de Lange, Ed F. Deprettere, Patrick Dewilde. 738-741 [doi]
- Toward Synthesis from English DescriptionsWalling R. Cyre. 742-745 [doi]
- Behavioral Modeling of Transmission Gates in VHDLSteven S. Leung. 746-749 [doi]
- COMP: A VHDL Composition SystemPaul R. Jordan, Ronald D. Williams. 750-753 [doi]
- Designer Controlled Behavioral SynthesisNikil D. Dutt, Daniel Gajski. 754-757 [doi]
- Fast Hypergraph PartitionAndrew B. Kahng. 762-766 [doi]
- An Evolution-Based Approach to Partitioning ASIC SystemsYoussef Saab, Vasant B. Rao. 767-770 [doi]
- Min-cost Partitioning on a Tree Structure and ApplicationsGopalakrishnan Vijayan. 771-774 [doi]
- Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection AlgorithmsThang Nguyen Bui, C. Heigham, Curt Jones, Frank Thomson Leighton. 775-778 [doi]
- Compaction of a Routed Channel on the Connection MachineS. Ganguly, Vijay Pitchumani. 779-782 [doi]
- Automatic Sizing of Power/Ground (P/G) Networks in VLSIRajiv Dutta, Malgorzata Marek-Sadowska. 783-786 [doi]
- DYNAJUST: An Efficient Automatic Routing Technique Optimizing Delay ConditionsYasuyuki Fujihara, Yutaka Sekiyama, Y. Ishibashi, M. Yanaka. 791-794 [doi]
- DTR: A Defect-Tolerant Routing AlgorithmAnucha Pitaksanonkul, Suchai Thanawastien, Chidchanok Lursinsap, J. A. Gandhi. 795-798 [doi]
- VIA Minimization by Layout ModificationKhe-Sing The, D. F. Wong, Jason Cong. 799-802 [doi]
- The Object-Oriented Integration Methodology of the Cadlab Work Station Design EnvironmentJulia Miller, K. Groning, Gerhard Schulz, C. White. 807-810 [doi]
- A Unified Design Representation Can WorkP. Kollaritsch, S. Lusky, D. Matzke, D. Smith, P. Stanford. 811-813 [doi]
- An Object-Oriented Datamodel for the VLSI Design System PLAYOUTErnst Siepmann, Gerhard Zimmermann. 814-817 [doi]
- Loop Optimization in Register-Transfer Scheduling for DSP-SystemsGert Goossens, Joos Vandewalle, Hugo De Man. 826-831 [doi]
- Semantics of a Hardware Design Language for Japanese StandardizationHiroto Yasuura, Nagisa Ishiura. 836-839 [doi]