Abstract is missing.
- Synthesis of Application-Specific Multiprocessor ArchitecturesShiv Prakash, Alice C. Parker. 8-13 [doi]
- Constraint improvements for MILP-based hardware synthesisLouis J. Hafer. 14-19 [doi]
- ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving ApproachYung-Ho Shih, Sung-Mo Kang. 20-25 [doi]
- ADAPTS: A Digital Transient Simulation Strategy for Integrated CircuitsAlexander D. Stein, Tuyen V. Nguyen, Binay J. George, Ronald A. Rohrer. 26-31 [doi]
- Efficient Simulation of Bipolar Digital ICsChandramouli Visweswariah, Ronald A. Rohrer. 32-37 [doi]
- Topological Routing in SURF: Generating a Rubber-Band sketchWayne Wei-Ming Dai, Tal Dayan, David Staepelaere. 39-44 [doi]
- Routability of a Rubber-Band SketchWayne Wei-Ming Dai, Raymond Kong, Masao Sato. 45-48 [doi]
- Novel Routing Schemes for IC Layout, Part I: Two-Layer Channel RoutingDeborah C. Wang. 49-53 [doi]
- Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing ProblemsSung-Chuan Fang, Kuo-En Chang, Wu-Shiung Feng, Sao-Jie Chen. 60-65 [doi]
- Logic Synthesis for Efficient Pseudoexhaustive TestabilityAndrzej Krasniewski. 66-72 [doi]
- Correlation-Reduced Scan-path Design To Improve Delay Fault CoverageWeiwei Mao, Michael D. Ciletti. 73-79 [doi]
- Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design MethodologyKwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer. 80-86 [doi]
- The Interdependence Between Delay-Optimization of Synthesized Networks and TestingThomas W. Williams, Bill Underwood, M. Ray Mercer. 87-92 [doi]
- A Technology Mapping Method Based On Perfect And Semi-Perfect MatchingsM. Crastes, K. Sakouti, Gabriele Saucier. 93-98 [doi]
- Layout Driven Technology MappingMassoud Pedram, Narasimha B. Bhat. 99-105 [doi]
- An ECL Logic Synthesis SystemVan Morgan, David Gregory. 106-111 [doi]
- Timing Optimization on Mapped CircuitsKo Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Shigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh. 112-117 [doi]
- Channel Density Reduction by Routing Over The CellsMin-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin. 120-125 [doi]
- New Algorithm for Over-the-Cell Channel Routing Using Vacant TerminalsNancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh. 126-131 [doi]
- Routing the 3-D ChipRichard J. Enbody, Gary Lynn, Kwee Heong Tan. 132-137 [doi]
- Algorithms for Fast, Memory Efficient Switch-Level Fault SimulationE. Vandris, Gerald E. Sobelman. 138-143 [doi]
- A System for Fault Diagnosis and Simulation of VHDL DescriptionsVijay Pitchumani, Pankaj Mayor, Nimish Radia. 144-150 [doi]
- Sequential Circuit Fault Simulation by Fault Information Tracing Algorithm: FITYoshihiro Kitamura. 151-154 [doi]
- Parallel Test Generation for Sequential Circuits on General-Purpose MultiprocessorsSrinivas Patil, Prithviraj Banerjee, Janak H. Patel. 155-159 [doi]
- On Removing Redundancy in Sequential CircuitsKwang-Ting Cheng. 164-169 [doi]
- A Framework for Satisfying Input and Output Encoding ConstraintsAlexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 170-175 [doi]
- A Unified Approach to Input-Output Encoding for FSM State AssignmentMaciej J. Ciesielski, Jia-Jye Shen, Marc Davio. 176-181 [doi]
- FSM Decomposition Revisited: Algebraic Structure Theory Applied to MCNC Benchmark FSMsMartin Geiger, Thomas Müller-Wipperfürth. 182-185 [doi]
- Intellectual Property (Panel Abstract)Michael C. McFarland. 186
- A CAD System for the Design of Field Programmable Gate ArraysDwight D. Hill. 187-192 [doi]
- Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe ComputersHidekazu Terai, Fumio Goto, Katsuro Wakai, Tokinori Kozawa, Mitsugu Edagawa, Satoshi Hososaka, Masahiro Hashimoto. 193-198 [doi]
- SIDECAR: Design Support for ReliabilityCharles R. Yount, Daniel P. Siewiorek. 199-204 [doi]
- Automatic Generation of Compiled Simulations through Program SpecializationWing Yee Au, Daniel Weise, Scott Seligman. 205-210 [doi]
- Utilizing Logic Information in Multi-Level Timing SimulationMarko P. Chew, Andrzej J. Strojwas. 215-218 [doi]
- Mapping Switch-Level Simulation onto Gate-Level Hardware AcceleratorsAlok Jain, Randal E. Bryant. 219-222 [doi]
- Breaking the Barrier of Parallel Simulation of Digital SystemsJack V. Briner Jr., John L. Ellis, Gershon Kedem. 223-226 [doi]
- Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAsRobert J. Francis, Jonathan Rose, Zvonko G. Vranesic. 227-233 [doi]
- Technology Mapping for Electrically Programmable Gate ArraysSilvia Ercolani, Giovanni De Micheli. 234-239 [doi]
- Xmap: A Technology Mapper for Table-Lookup Field-Programmable Gate ArraysKevin Karplus. 240-243 [doi]
- Amap: A Technology Mapper for Selector-Based Field-Programmable Gate ArraysKevin Karplus. 244-247 [doi]
- A Heuristic Method for FPGA Technology Mapping Based on the Edge VisibilityNam Sung Woo. 248-251 [doi]
- What is Design for Manufacturability (DFM)? (Panel Abstract)Wojciech Maly. 252
- Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe DesignYasushi Ogawa, Tsutomu Itoh, Yoshio Miki, Tatsuki Ishii, Yasuo Sato, Reiji Toyoshima. 253-258 [doi]
- Object Oriented Lisp Implementation of the CHEOPS VLSI Floor Planning and Routing SystemChristian Masson, Remy Escassut, Denis Barbier, Daniel Winer, Gregory Chevallier. 259-264 [doi]
- Benchmarks for Layout Synthesis - Evolution and Current StatusKrzysztof Kozminski. 265-270 [doi]
- A Design for Testability Scheme with Applications to Data Path SynthesisScott Chiu, Christos A. Papachristou. 271-277 [doi]
- Enhanced Controllability for ::::I::DDQ:::::: Test Sets Using Partial ScanTapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin. 278-281 [doi]
- ATPG Based on a Novel Grid-Addressable Latch ElementSusheel J. Chandra, Tom Ferry, Tushar Gheewala, Kerry Pierce. 282-286 [doi]
- Graph Partitioning for Concurrent Test Scheduling in VLSI CircuitChien-In Henry Chen. 287-290 [doi]
- Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic CircuitsDavid M. Wu, Charles E. Radke. 291-295 [doi]
- Automatic Synthesis of Asynchronous CircuitsKuan Jen Lin, Chen-Shang Lin. 296-301 [doi]
- Algorithms for Synthesis of Hazard-Free Asynchronous CircuitsLuciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli. 302-308 [doi]
- Synthesis of Multiple-Input Change Asynchronous Finite state MachinesMaureen Ladd, William P. Birmingham. 309-314 [doi]
- Framework Standards: How Important are They? (Panel Abstract)A. Richard Newton. 315
- A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow AlgorithmRobert C. Carden IV, Chung-Kuan Cheng. 316-321 [doi]
- High-Performance Clock Routing Based on Recursive Geometric AatchingAndrew B. Kahng, Jason Cong, Gabriel Robins. 322-327 [doi]
- On Minimizing the Number of L-Shaped ChannelsYang Cai, D. F. Wong. 328-334 [doi]
- A General Multi-Layer Area RouterMohankumar Guruswamy, D. F. Wong. 335-340 [doi]
- On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault ModelIrith Pomeranz, Sudhakar M. Reddy. 341-346 [doi]
- Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level CircuitsStephen Pateras, Janusz Rajski. 347-352 [doi]
- A Transitive Closure Based Algorithm for Test GenerationSrimat T. Chakradhar, Vishwani D. Agrawal. 353-358 [doi]
- A Synthesis-Based Test Generation and Compaction Algorithm for MultifaultsSrinivas Devadas, Kurt Keutzer, Sharad Malik. 359-365 [doi]
- Control Optimization Based on Resynchronization of OperationsDavid C. Ku, Dave Filo, Giovanni De Micheli. 366-371 [doi]
- A Unified Approach for the Synthesis of Self-Testable Finite State MachinesBernhard Eschermann, Hans-Joachim Wunderlich. 372-377 [doi]
- Automated Micro-Roll-back Self-Recovery SynthesisVijay Raghavendra, Chidchanok Lursinsap. 385-390 [doi]
- Proof-Aided Design of Verified HardwareHolger Busch, Gerd Venzl. 391-396 [doi]
- Formal Hardware Verification by Symbolic Ternary Trajectory EvaluationRandal E. Bryant, Derek L. Beatty, Carl-Johan H. Seger. 397-402 [doi]
- Representing Circuits More Efficiently in Symbolic Model CheckingJerry R. Burch, Edmund M. Clarke, David E. Long. 403-407 [doi]
- Using BDDs to Verify MultipliersJerry R. Burch. 408-412 [doi]
- Breadth-First Manipulation of SBDD of Boolean Functions for Vector ProcessingHiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima. 413-416 [doi]
- Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision DiagramsKenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer. 417-420 [doi]
- A General Purpose Multiple Way Partitioning AlgorithmChing-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin. 421-426 [doi]
- Analytical Placement: A Linear or a Quadratic Objective Function?Georg Sigl, Konrad Doll, Frank M. Johannes. 427-432 [doi]
- Branch-and-Bound Placement for Building Block LayoutHidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru. 433-439 [doi]
- A Probabilistic Testability Measure for Delay FaultsWen Ching Wu, Chung-Len Lee. 440-445 [doi]
- Testability of Asynchronous Timed Control Circuits with Delay AssumptionsPeter A. Beerel, Teresa H. Y. Meng. 446-451 [doi]
- A Branching Process Model for Observability Analysis of Combinational CircuitsSarma Sastry, Amitava Majumdar. 452-457 [doi]
- A Resynthesis Approach for Network OptimizationKuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita. 458-463 [doi]
- Logic Optimization of MOS NetworksJohnson Chan Limqueco, Saburo Muroga. 464-469 [doi]
- Logic Minimization using Two-column Rectangle ReplacementSøren Søe, Kevin Karplus. 470-473 [doi]
- Are Formal Methods in Design for Real? (Panel Abstract)Gerd Venzl. 474
- Flexible Transistor Matrix (FTM)King C. Ho, Sarma Sastry. 475-480 [doi]
- An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic GenerationChi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu. 481-486 [doi]
- Exact Width and Height Minimization of CMOS CellsRobert L. Maziasz, John P. Hayes. 487-493 [doi]
- Optimal Ordering of Analog Integrated Circuit Tests to Minimize Test TimeScott D. Huss, Ronald S. Gyurcsik. 494-499 [doi]
- A Constraint Based Approach to Automatic Design of Analog CellsLouis-Oliver Donzelle, Pierre-François Dubois, B. Hennion, J. Parissis, P. Senn. 506-509 [doi]
- A Layout Improvement Method Based on Constraint Propagation for Analog LSI sMasato Mogaki, Naoki Kato, Naomi Shimada, Yuriko Yamada. 510-513 [doi]
- CHOP: A Constraint-Driven System-Level PartitionerKayhan Küçükçakar, Alice C. Parker. 514-519 [doi]
- The Effects of Physical Design Characteristics on the Area-Performance Tradeoff CurveAlice C. Parker, Pravil Gupta, Agha Hussain. 530-534 [doi]
- An Efficient Parallel Critical Path AlgorithmLi-Ren Liu, David Hung-Chang Du, Hsi-Chuan Chen. 535-540 [doi]
- Incremental Techniques for the Identification of Statically Sensitizable Critical PathsYun-Cheng Ju, Resve A. Saleh. 541-546 [doi]
- Critical Path Selection for Performance OptimizationHsi-Chuan Chen, David Hung-Chang Du, Li-Ren Liu. 547-550 [doi]
- Timing Verification on a 1.2M-Device Full-Custom CMOS DesignJengwei Pan, Larry L. Biro, Joel Grodstein, William J. Grundmann, Yao-Tsung Yen. 551-554 [doi]
- RICE: Rapid Interconnect Circuit EvaluatorCurtis L. Ratzlaff, Nanda Gopal, Lawrence T. Pillage. 555-560 [doi]
- A New Nonlinear Driver Model for Interconnect AnalysisVivek Raghavan, Ronald A. Rohrer. 561-566 [doi]
- Propagation Delay Calculation for Interconnection Nets on Printed Circuit Boards by Reflected WavesHeinz Mattes, Wolfgang Weisenseel, Gerhard Bischof, Reimund Dachauer. 567-572 [doi]
- Linking TCAD to EDA - Benefits and IssuesGoodwin R. Chin, Walter C. Dietrich Jr., Duane S. Boning, Alexander S. Wong, Andrew R. Neureuther, Robert W. Dutton. 573-578 [doi]
- GOALSERVER: A Multiobjective Design Optimization Tool for IC Fabrication ProcessLifeng Wu, Zhilian Yang, Zhiping Yu, Zhijian Li. 585-590 [doi]
- Data-Path Synthesis Using Path AnalysisReinaldo A. Bergamaschi, Raul Camposano, Michael Payer. 591-596 [doi]
- Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP ApplicationsStefaan Note, Werner Geurts, Francky Catthoor, Hugo De Man. 597-602 [doi]
- Datapath Scheduling for Two-Level PipeliningC. Y. Roger Chen, Michael Z. Moricz. 603-606 [doi]
- Relevant Issues in High-Level Connectivity SynthesisBarry M. Pangrle, Forrest Brewer, Donald Lobo, Andrew Seawright. 607-610 [doi]
- Testability Solutions: Who Really Wants Them? (Panel Abstract)Alberto L. Sangiovanni-Vincentelli. 611
- The Role of Timing Verification in Layout SynthesisJacques Benkoski, Andrzej J. Strojwas. 612-619 [doi]
- An Analytic Net Weighting Approach for Performance Optimization in Circuit PlacementRen-Song Tsay, Jürgen Koehl. 620-625 [doi]
- Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven PlacementSuphachai Sutanthavibul, Eugene Shragowitz. 632-635 [doi]
- Transition Density, A Stochastic Measure of Activity in Digital CircuitsFarid N. Najm. 644-649 [doi]
- Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic CircuitsYutaka Deguchi, Nagisa Ishiura, Shuzo Yajima. 650-655 [doi]
- OEsim: A Simulator for Timing BehaviorTod Amon, Gaetano Borriello. 656-661 [doi]
- CLOVER: A Timing Constraints Verification SystemDimitris Doukas, Andrea S. LaPaugh. 662-667 [doi]
- 3D Scheduling: High-Level Synthesis with FloorplanningJen-Pin Weng, Alice C. Parker. 668-673 [doi]
- Bottom Up Synthesis Based on Fuzzy SchedulesTai A. Ly, Jack T. Mowchenko. 674-679 [doi]
- Fast and Near Optimal Scheduling in Automatic Data Path AynthesisIn-Cheol Park, Chong-Min Kyung. 680-685 [doi]
- Empirical Evaluation of Some High-Level Synthesis Scheduling HeuristicsRajiv Jain, Ashutosh Mujumdar, Alok Sharma, Hueymin Wang. 686-689 [doi]
- Sizing Synchronization Queues: A Case Study in Higher Level SynthesisTod Amon, Gaetano Borriello. 690-693 [doi]
- Design Flow Management in the NELSIS CAD FrameworkK. Olav ten Bosch, Peter Bingley, Pieter van der Wolf. 711-716 [doi]
- A Two-Dimensional Topological Compactor With Octagonal GeometryPaul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya. 727-731 [doi]
- On Minimal Closure Constraint Generation for Symbolic Cell AssemblyDebaprosad Dutt, Chi-Yuan Lo. 736-739 [doi]
- Efficient Transient Simulation of Lossy InterconnectJaijeet S. Roychowdhury, Donald O. Pederson. 740-745 [doi]
- Modeling and Simulation of High-Frequency Integrated Circuits Based on Scattering ParametersAndrew T. Yang, C. H. Chan, Jack T. Yao, R. R. Daniels, J. P. Harrang. 752-757 [doi]
- Minimizing the Number of Delay Buffers in the Synchronization of Pipelined SystemsXiaobo Hu, Ronald G. Harber, Steven C. Bass. 758-763 [doi]
- Scheduling for Functional Pipelining and Loop WindingCheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin. 764-769 [doi]
- Incremental Tree Height Reduction for High Level SynthesisAlexandru Nicolau, Roni Potasman. 770-774 [doi]
- Redundant Operator Creation: A Scheduling Optimization TechniqueDonald Lobo, Barry M. Pangrle. 775-778 [doi]
- Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract)Jonathan Rose. 779