Abstract is missing.
- Design without Borders - A Tribute to the Legacy of A. Richard NewtonJan M. Rabaey. [doi]
- Designing a New Automotive DNALawrence D. Burns. [doi]
- Perspective of the Future Semiconductor Industry: Challenges and SolutionsOh-Hyun Kwon. [doi]
- Trusted Hardware: Can It Be Trustworthy?Cynthia E. Irvine, Karl N. Levitt. 1-4 [doi]
- Trusted Design in FPGAsSteven Trimberger. 5-8 [doi]
- Physical Unclonable Functions for Device Authentication and Secret Key GenerationG. Edward Suh, Srinivas Devadas. 9-14 [doi]
- Side-Channel Attack PitfallsKris Tiri. 15-20 [doi]
- Megatrends and EDA 2017Francine Bacchini, Greg Spirakis, Juan Antonio Carballo, Kurt Keutzer, Aart J. de Geus, Fu-Chieh Hsu, Kazu Yamada. 21-22 [doi]
- System-Level Design Flow Based on a Functional Reference for HW and SWWalter H. Tibboel, Víctor Reyes, Martin Klompstra, Dennis Alders. 23-28 [doi]
- Model-driven Validation of SystemC DesignsHiren D. Patel, Sandeep K. Shukla. 29-34 [doi]
- Language Extensions to SystemC: Process Control ConstructsBishnupriya Bhattacharya, John Rose, Stuart Swan. 35-38 [doi]
- Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya. 39-42 [doi]
- Design of Rotary Clock Based CircuitsZhengtao Yu, Xun Liu. 43-48 [doi]
- Escape Routing For Dense Pin Clusters In Integrated CircuitsMuhammet Mustafa Ozdal. 49-54 [doi]
- TROY: Track Router with Yield-driven Wire PlanningMinsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan. 55-58 [doi]
- IPR: An Integrated Placement and Routing AlgorithmMin Pan, Chris C. N. Chu. 59-62 [doi]
- An Effective Guidance Strategy for Abstraction-Guided SimulationFlavio M. de Paula, Alan J. Hu. 63-68 [doi]
- Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance ValidationLovleen Bhatia, Jayesh Gaur, Praveen Tiwari, Raj S. Mitra, Sunil H. Matange. 69-74 [doi]
- Synthesizing SVA Local Variables for Formal VerificationJiang Long, Andrew Seawright. 75-80 [doi]
- Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power MinimizationDe-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang. 81-86 [doi]
- Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage ShiftJie Gu, Sachin S. Sapatnekar, Chris H. Kim. 87-92 [doi]
- Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die CorrelationKhaled R. Heloue, Navid Azizi, Farid N. Najm. 93-98 [doi]
- Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling LeakageTao Li, Zhiping Yu. 99-102 [doi]
- Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential CircuitsJun Seomun, Jaehyun Kim, Youngsoo Shin. 103-106 [doi]
- Making Manufacturing Work For YouSrikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian. 107-108 [doi]
- Voltage-Frequency Island Partitioning for GALS-based Networks-on-ChipÜmit Y. Ogras, Radu Marculescu, Puru Choudhary, Diana Marculescu. 110-115 [doi]
- Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GTThéodore Marescaux, Henk Corporaal. 116-121 [doi]
- Layered Switching for Networks on ChipZhonghai Lu, Ming Liu, Axel Jantsch. 122-127 [doi]
- Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage IslandsLap-Fai Leung, Chi-Ying Tsui. 128-131 [doi]
- The Case for Low-Power Photonic Networks on ChipAssaf Shacham, Keren Bergman, Luca P. Carloni. 132-135 [doi]
- Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition EquationsShweta Srivastava, Jaijeet S. Roychowdhury. 136-141 [doi]
- PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator MacromodelsZhichun Wang, Xiaolue Lai, Jaijeet S. Roychowdhury. 142-147 [doi]
- Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing AnalysisAnand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan. 148-153 [doi]
- Simulating Improbable EventsSuwen Yang, Mark R. Greenstreet. 154-157 [doi]
- SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC CircuitsBoyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy. 158-161 [doi]
- On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic NoiseMin Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan. 162-167 [doi]
- Optimal Selection of Voltage Regulator Modules in a Power Delivery NetworkBehnam Amelifard, Massoud Pedram. 168-173 [doi]
- Top-k Aggressors Sets in Delay Noise AnalysisRavikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer. 174-179 [doi]
- A New Twisted Differential Line Structure in Global Bus DesignZhanyuan Jiang, Shiyan Hu, Weiping Shi. 180-183 [doi]
- Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock SkewAbinash Roy, Noha H. Mahmoud, Masud H. Chowdhury. 184-187 [doi]
- Formal Techniques for SystemC Verification; Position PaperMoshe Y. Vardi. 188-192 [doi]
- Design for Verification in System-level Models and RTLAnmol Mathur, Venkat Krishnaswamy. 193-198 [doi]
- Verification Methodologies in a TLM-to-RTL Design FlowAtsushi Kasuya, Tesh Tesfaye. 199-204 [doi]
- Memory Modeling in ESL-RTL Equivalence CheckingAlfred Kölbl, Jerry R. Burch, Carl Pixley. 205-209 [doi]
- Early Power-Aware Design & Validation: Myth or Reality?Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis. 210-211 [doi]
- Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling DesignYuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo. 212-217 [doi]
- A System For Coarse Grained Memory Protection In Tiny Embedded ProcessorsRam Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani B. Srivastava. 218-223 [doi]
- Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processorsHakduran Koc, Mahmut T. Kandemir, Ehat Ercanli, Ozcan Ozturk. 224-229 [doi]
- A Memory-Conscious Code Parallelization SchemeLiping Xue, Ozcan Ozturk, Mahmut T. Kandemir. 230-233 [doi]
- A Self-Tuning Configurable CacheAnn Gordon-Ross, Frank Vahid. 234-237 [doi]
- Comparative Analysis of Conventional and Statistical Design TechniquesSteven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James Tschanz, Vivek De. 238-243 [doi]
- Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension ReductionZhuo Feng, Peng Li, Yaping Zhan. 244-249 [doi]
- Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation SourcesLerong Cheng, Jinjun Xiong, Lei He. 250-255 [doi]
- Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear FittingAmith Singhee, Rob A. Rutenbar. 256-261 [doi]
- Chip Multi-Processor GeneratorAlex Solomatnikov, Amin Firoozshahian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Zain Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz. 262-263 [doi]
- The Case for the Precision Timed (PRET) MachineStephen A. Edwards, Edward A. Lee. 264-265 [doi]
- Quantum-Like Effects in Network-on-Chip Buffers BehaviorPaul Bogdan, Radu Marculescu. 266-267 [doi]
- CAD-based Security, Cryptography, and Digital Rights ManagementFarinaz Koushanfar, Miodrag Potkonjak. 268-269 [doi]
- Line-End Shortening is Not Always a FailurePuneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester. 270-271 [doi]
- You Can Get There From Here: Connectivity of Random Graphs on GridsSteven P. Levitan. 272-273 [doi]
- High Performance and Low Power Electronics on Flexible SubstrateJing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy. 274-275 [doi]
- Novel CNTFET-based Reconfigurable Logic Gate DesignJ. Liu, Ian O Connor, David Navarro, Frédéric Gaffiot. 276-277 [doi]
- Period Optimization for Hard Real-time Distributed Automotive SystemsAbhijit Davare, Qi Zhu, Marco Di Natale, Claudio Pinello, Sri Kanajan, Alberto L. Sangiovanni-Vincentelli. 278-283 [doi]
- Performance Analysis of FlexRay-based ECU NetworksAndrei Hagiescu, Unmesh D. Bordoloi, Samarjit Chakraborty, Prahladavaradan Sampath, P. Vignesh V. Ganesan, Sethu Ramesh. 284-289 [doi]
- Experimental Jitter Analysis in a FlexCAN Based Drive-by-Wire Automotive ApplicationJuan R. Pimentel, Jason Paskvan. 290-293 [doi]
- Optimization of Static Task and Bus Access Schedules for Time-Triggered Distributed Embedded Systems with Model-CheckingZonghua Gu, Xiuqiang He, Mingxuan Yuan. 294-299 [doi]
- NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable ArchitectureWei Zhang, Li Shang, Niraj K. Jha. 300-305 [doi]
- Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power ApplicationsHamed F. Dadgour, Kaustav Banerjee. 306-311 [doi]
- Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling TransistorsChangyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Robert G. Knobel. 312-317 [doi]
- GlitchMap: An FPGA Technology Mapper for Low Power Considering GlitchesLei Cheng, Deming Chen, Martin D. F. Wong. 318-323 [doi]
- Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA CircuitsTomasz S. Czajkowski, Stephen Dean Brown. 324-329 [doi]
- Single-Event-Upset (SEU) Awareness in FPGA RoutingS. Golshan, Elaheh Bozorgzadeh. 330-333 [doi]
- Enhancing FPGA Performance for Arithmetic CircuitsPhilip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar. 334-337 [doi]
- Fast Min-Cost Buffer Insertion under Process VariationsRuiming Chen, Hai Zhou. 338-343 [doi]
- Exact Combinatorial Optimization Methods for Physical Design of Regular Logic BricksBrian Taylor, Larry T. Pileggi. 344-349 [doi]
- Concurrent Wire Spreading, Widening, and FillingOlivier Rizzo, Hanno Melzner. 350-353 [doi]
- Modeling Litho-Constrained Design LayoutMin-Chun Tsai, Daniel Zhang, Zongwu Tang. 354-357 [doi]
- Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ MeasurementKunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy. 358-363 [doi]
- The Impact of NBTI on the Performance of Combinational and Sequential CircuitsWenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao. 364-369 [doi]
- NBTI-Aware Synthesis of Digital CircuitsSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. 370-375 [doi]
- There Is More Than Moore In Automotive ... Hartmut Hiller. 376 [doi]
- Modeling Safe Operating Area in Hardware Description LanguagesLeonid B. Goldgeisser, Ernst Christen, Zhichao Deng. 377-382 [doi]
- Autonomous Automobiles: Developing Cars That Drive ThemselvesDave Ferguson. 383 [doi]
- Design-Silicon Timing Correlation A Data Mining PerspectiveLi-C. Wang, Pouria Bastani, Magdy S. Abadir. 384-389 [doi]
- Silicon Speedpath Measurement and Feedback into EDA flowsKip Killpack, Chandramouli V. Kashyap, Eli Chiprout. 390-395 [doi]
- Characterizing Process Variation in Nanometer CMOSKanak Agarwal, Sani R. Nassif. 396-399 [doi]
- On-Chip Measurements Complementary to Design Flow for Integrity in SoCsMakoto Nagata. 400-403 [doi]
- Progressive Decomposition: A Heuristic to Structure Arithmetic CircuitsAjay K. Verma, Philip Brisk, Paolo Ienne. 404-409 [doi]
- Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive SystemRebecca L. Collins, Luca P. Carloni. 410-415 [doi]
- Synchronous Elastic Circuits with Early Evaluation and Token CounterflowJordi Cortadella, Michael Kishinevsky. 416-419 [doi]
- Optimization of Area in Digital FIR Filters using Gate-Level MetricsLevent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José C. Monteiro. 420-423 [doi]
- Parameter Finding Methods for Oscillators with a Specified Oscillation FrequencyIgor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram. 424-429 [doi]
- Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked LoopsHenry H. Y. Chan, Zeljko Zilic. 430-435 [doi]
- Accelerating Harmonic Balance Simulation Using Efficient Parallelizable Hierarchical PreconditioningWei Dong, Peng Li. 436-439 [doi]
- Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device MismatchJaeha Kim, Kevin D. Jones, Mark A. Horowitz. 440-443 [doi]
- TLM: Crossing Over From Buzz To AdoptionFrancine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil. 444-445 [doi]
- Electronics: The New Differential in the Automotive IndustryNick Smith, Andrew Chien, Christopher Hegarty, Walden C. Rhines, Alberto L. Sangiovanni-Vincentelli, Frank Winters. 446 [doi]
- MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size DesignsTung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu. 447-452 [doi]
- RQL: Global Placement via Relaxed Quadratic Spreading and LinearizationNatarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu. 453-458 [doi]
- Improving Voltage Assignment by Outlier Detection and Incremental PlacementHuaizhi Wu, Martin D. F. Wong. 459-464 [doi]
- Analog Placement Based on Novel Symmetry-Island FormulationPo-Hung Lin, Shyh-Chang Lin. 465-470 [doi]
- Modeling the Function Cache for Worst-Case Execution Time AnalysisRaimund Kirner, Martin Schoeberl. 471-476 [doi]
- An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC IntegrationChung-Fu Kao, Ing-Jer Huang, Chi-Hung Lin. 477-482 [doi]
- Hardware Support for Secure Processing in Embedded SystemsShufu Mao, Tilman Wolf. 483-488 [doi]
- RIJID: Random Code Injection to Mask Power Analysis based Side Channel AttacksJude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran. 489-492 [doi]
- Compact State Machines for High Performance Pattern MatchingPiti Piyachon, Yan Luo. 493-496 [doi]
- Confidence Scalable Post-Silicon Statistical Delay Prediction under Process VariationsQunzeng Liu, Sachin S. Sapatnekar. 497-502 [doi]
- Statistical Framework for Technology-Model-Product Co-Design and ConvergenceChoongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski. 503-508 [doi]
- Extraction of Statistical Timing Profiles Using Test DataYing-Yen Chen, Jing-Jia Liou. 509-514 [doi]
- An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global WiresKrishnan Sundaresan, Nihar R. Mahapatra. 515-520 [doi]
- Scan Test Planning for Power ReductionMichael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra. 521-526 [doi]
- Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan TestingXiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja. 527-532 [doi]
- Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC DesignNisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram. 533-538 [doi]
- New Test Data Decompressor for Low Power ApplicationsGrzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer. 539-544 [doi]
- Automotive Software IntegrationRazvan Racu, Arne Hamann, Rolf Ernst, Kai Richter. 545-550 [doi]
- Virtual Platforms and Timing Analysis: Status, Challenges and Future DirectionsMarco Di Natale. 551-555 [doi]
- Computer-aided Architecture Design & Optimized Implementation of Distributed Automotive EE SystemsAntal Rajnak, Ajay Kumar. 556-561 [doi]
- Interconnects in the Third Dimension: Design Challenges for 3D ICsKerry Bernstein, Paul Andry, Jerome Cann, Philip G. Emma, David Greenberg, Wilfried Haensch, Mike Ignatowski, Steve Koester, John Magerlein, Ruchir Puri, Albert M. Young. 562-567 [doi]
- Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube InterconnectsAzad Naeemi, Reza Sarvari, James D. Meindl. 568-573 [doi]
- Micro-Photonic Interconnects: Characteristics, Possibilities and LimitationsJaijeet S. Roychowdhury. 574-575 [doi]
- CAD Implications of New Interconnect TechnologiesLouis Scheffer. 576-581 [doi]
- Alembic: An Efficient Algorithm for CNF PreprocessingHyoJung Han, Fabio Somenzi. 582-587 [doi]
- EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL ProcedureShujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao. 588-593 [doi]
- On-The-Fly Resolve Trace MinimizationOhad Shacham, Karen Yorav. 594-599 [doi]
- On Resolution Proofs for Combinational EquivalenceSatrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann. 600-605 [doi]
- An Integer Linear Programming Based Routing Algorithm for Flip-Chip DesignJia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang. 606-611 [doi]
- Computationally Efficient Power Integrity Simulation for System-on-Package ApplicationsKrishna Bharath, Ege Engin, Madhavan Swaminathan, Kazuhide Uriu, Toru Yamada. 612-617 [doi]
- Off-chip Decoupling Capacitor Allocation for Chip Package Co-DesignHao Yu, Chunta Chu, Lei He. 618-621 [doi]
- Scalability of 3D-Integrated Arithmetic Units in High-Performance MicroprocessorsKiran Puttaswamy, Gabriel H. Loh. 622-625 [doi]
- Placement of 3D ICs with Thermal and Interlayer Via ConsiderationsBrent Goplen, Sachin S. Sapatnekar. 626-631 [doi]
- Corezilla: Build and Tame the Multicore Beast?Lauren Sarno, Wen-mei W. Hwu, Craig Lund, Markus Levy, James R. Larus, James Reinders, Gordon Cameron, Chris Lennard, Takashi Yoshimori. 632-633 [doi]
- Synthetic biology: from bacteria to stem cellsRon Weiss. 634-635 [doi]
- Engineering synthetic killer circuits in bacteriaLingchong You. 636-637 [doi]
- Programming Living Cells to Function as Massively Parallel ComputersJeffrey J. Tabor. 638-639 [doi]
- Synthesizing Stochasticity in Biochemical SystemsBrian Fett, Jehoshua Bruck, Marc D. Riedel. 640-645 [doi]
- Instruction Splitting for Efficient Code CompressionTalal Bonny, Jörg Henkel. 646-651 [doi]
- An Embedded Coherent-Multithreading Multimedia Processor and Its Programming ModelJui-Chin Chu, Wei-Chun Ku, Shu-Hsuan Chou, Tien-Fu Chen, Jiun-In Guo. 652-657 [doi]
- Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow GraphsMaarten Wiggers, Marco Bekooij, Gerard J. M. Smit. 658-663 [doi]
- Energy-Aware Scheduling for Real-Time Multiprocessor Systems with Uncertain Task Execution TimeChangjiu Xian, Yung-Hsiang Lu, Zhiyuan Li. 664-669 [doi]
- A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-ChipPraveen Bhojwani, Rabi N. Mahapatra. 670-675 [doi]
- SOC Test Architecture Optimization for Signal Integrity Faults on Core-External InterconnectsQiang Xu, Yubin Zhang, Krishnendu Chakrabarty. 676-681 [doi]
- A DFT Method for Time Expansion Model at Register Transfer LevelHiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara. 682-687 [doi]
- Test Generation in the Presence of Timing Exceptions and ConstraintsDhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski. 688-693 [doi]
- Analysis and Optimization of Sleep Modes in Subthreshold Circuit DesignMingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw. 694-699 [doi]
- Nanometer Device Scaling in Subthreshold CircuitsScott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw. 700-705 [doi]
- Efficient Modeling Techniques for Dynamic Voltage Drop AnalysisHedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke. 706-711 [doi]
- On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson MethodAshesh Rastogi, Wei Chen, Sandip Kundu. 712-715 [doi]
- Energy-Aware Data Compression for Multi-Level Cell (MLC) Flash MemoryYongsoo Joo, Youngjin Cho, Donghwa Shin, Naehyuck Chang. 716-719 [doi]
- Shared Resource Access Attributes for High-Level Contention ModelsAlex Bobrek, JoAnn M. Paul, Donald E. Thomas. 720-725 [doi]
- A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media DevicesAkash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha. 726-731 [doi]
- Automatic Cache Tuning for Energy-Efficiency using Local Regression ModelingPeter Hallschmid, Resve Saleh. 732-737 [doi]
- Reducing Data-Memory Footprint of Multimedia Applications by Delay RedistributionBalaji Raman, Samarjit Chakraborty, Wei Tsang Ooi, Santanu Dutta. 738-743 [doi]
- Verification Coverage: When is Enough, Enough?Francine Bacchini, Alan J. Hu, Tom Fitzpatrick, Rajeev Ranjan, David Lacey, Mercedes Tan, Andrew Piziali, Avi Ziv. 744-745 [doi]
- Thousand Core ChipsA Technology PerspectiveShekhar Borkar. 746-749 [doi]
- The KILL Rule for MulticoreAnant Agarwal, Markus Levy. 750-753 [doi]
- Implicitly Parallel Programming Models for Thousand-Core MicroprocessorsWen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel. 754-759 [doi]
- Multi-Core Design Automation ChallengesJohn A. Darringer. 760-764 [doi]
- Interconnect and Communication Synthesis for Distributed Register-File MicroarchitectureKyoung-Hwan Lim, YongHwan Kim, Taewhan Kim. 765-770 [doi]
- Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable ArchitecturesSudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera. 771-776 [doi]
- Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow GraphsSander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal. 777-782 [doi]
- Global Critical Path: A Tool for System-Level Timing AnalysisGirish Venkataramani, Mihai Budiu, Tiberiu Chelcea, Seth Copen Goldstein. 783-786 [doi]
- Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC SpecificationPramod Chandraiah, Rainer Dömer. 787-790 [doi]
- RISPP: Rotating Instruction Set Processing PlatformLars Bauer, Muhammad Shafique, Simon Kramer 0002, Jörg Henkel. 791-796 [doi]
- ASIP Instruction Encoding for Energy and Area ReductionPaul Morgan, Richard Taylor. 797-800 [doi]
- Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor ArchitecturesChristopher Ostler, Karam S. Chatha. 801-804 [doi]
- Program Mapping onto Network Processors by Recursive Bipartitioning and RefiningJia Yu, Jingnan Yao, Laxmi N. Bhuyan, Jun Yang. 805-810 [doi]
- Design Methodology for Pipelined Heterogeneous Multiprocessor SystemSeng Lin Shee, Sri Parameswaran. 811-816 [doi]
- A General Framework for Spatial Correlation Modeling in VLSI DesignFrank Liu. 817-822 [doi]
- Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit SimulationRitu Singhal, Asha Balijepalli, Anupama Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao. 823-828 [doi]
- A Framework for Accounting for Process Model Uncertainty in Statistical Static Timing AnalysisGuo Yu, Wei Dong, Zhuo Feng, Peng Li. 829-834 [doi]
- Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element MethodYing Zhou, Zhuo Li, Weiping Shi. 835-840 [doi]
- A Unified Approach to Canonical Form-based Boolean MatchingGiovanni Agosta, Francesco Bruschi, Gerardo Pelosi, Donatella Sciuto. 841-846 [doi]
- Gate Sizing For Cell Library-Based DesignsShiyan Hu, Mahesh Ketkar, Jiang Hu. 847-852 [doi]
- Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based OptimizationXiaoji Ye, Yaping Zhan, Peng Li. 853-858 [doi]
- Techniques for Effective Distributed Physical SynthesisFreddy Y. C. Mang, Wenting Hou, Pei-Hsin Ho. 859-864 [doi]
- SODA: Sensitivity Based Optimization of Disk ArchitectureYan Zhang, Sudhanva Gurumurthi, Mircea R. Stan. 865-870 [doi]
- Dynamic Power Management with Hybrid Power SourcesJianli Zhuo, Chaitali Chakrabarti, Kyungsoo Lee, Naehyuck Chang. 871-876 [doi]
- System-on-Chip Power Management Considering Leakage Power VariationsSaumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey. 877-882 [doi]
- Accelerating System-on-Chip Power Analysis Using Hybrid Power EstimationMohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan. 883-886 [doi]
- A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply VoltagesHung-Yi Liu, Wan-Ping Lee, Yao-Wen Chang. 887-890 [doi]
- Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test GenerationShady Copty, Itai Jaeger, Yoav Katz, Michael Vinov. 891-895 [doi]
- Automatic Verification of External Interrupt Behaviors for Microprocessor DesignFu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang. 896-901 [doi]
- A Framework for the Validation of Processor Architecture ComplianceAllon Adir, Sigal Asaf, Laurent Fournier, Itai Jaeger, Ofer Peled. 902-905 [doi]
- Functional Verification of SiCortex Multiprocessor System-on-a-ChipOleg Petlin, Wilson Snyder. 906-909 [doi]
- DDBDD: Delay-Driven BDD Synthesis for FPGAsLei Cheng, Deming Chen, Martin D. F. Wong. 910-915 [doi]
- FlexWAFE - A High-end Real-Time Stream Processing Library for FPGAsAmilcar do Carmo Lucas, Sven Heithecker, Rolf Ernst. 916-921 [doi]
- How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAsCatherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu. 922-927 [doi]
- Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF CircuitsXin Li, Lawrence T. Pileggi. 928-933 [doi]
- Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked LoopKunhyuk Kang, Kee-Jong Kim, Kaushik Roy. 934-939 [doi]
- Parameterized Macromodeling for Analog System-Level Design ExplorationJian Wang, Xin Li, Lawrence T. Pileggi. 940-943 [doi]
- Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit TopologiesTrent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert. 944-947 [doi]
- Integrated Droplet Routing in the Synthesis of Microfluidic BiochipsTao Xu, Krishnendu Chakrabarty. 948-953 [doi]
- OPC-Free and Minimally Irregular IC Design StyleWojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska. 954-957 [doi]
- Automated Design of Misaligned-Carbon-Nanotube-Immune CircuitsNishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra. 958-961 [doi]
- Quantum Circuit Placement: Optimizing Qubit-to-qubit Interactions through Mapping Quantum Circuits into a Physical ExperimentDmitri Maslov, Sean M. Falconer, Michele Mosca. 962-965 [doi]
- Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si: H TFT Scan DriverTsung-Ching Huang, Huai-Yuan Tseng, Chen-Pang Kung, Kwang-Ting Cheng. 966-969 [doi]
- Clock Period Minimization with Minimum Delay InsertionShih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh. 970-975 [doi]
- An Efficient Mechanism for Performance Optimization of Variable-Latency DesignsYu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska. 976-981 [doi]
- A Fully-Automated Desynchronization Flow for Synchronous CircuitsNikolaos Andrikos, Luciano Lavagno, Davide Pandini, Christos P. Sotiriou. 982-985 [doi]
- Self-Resetting Latches for Asynchronous Micro-PipelinesTiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein. 986-989 [doi]
- IP Exchange: I ll Show You Mine if You Show Me YoursLauren Sarno, Ron Wilson, Soo-Kwan Eo, Laurent Lestringand, John Goodenough, Guri Stark, Serge Leef, Dave Witt. 990-991 [doi]