Table of Contents

• CAD for military systems, an essential link to LSI, VLSI and VHSIC technologyRandolph Reitmeyer Jr.. 3-12 [doi]
• Recent developments in representation in the science of designCharles M. Eastman. 13-21 [doi]
• The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routingG. Persky, C. Enger, D. M. Selove. 22-28 [doi]
• An algorithm for searching shortest path by propagating wave fronts in four quadrantsXiong Ji-Guang, Tokinori Kozawa. 29-36 [doi]
• Computation of power supply nets in VLSI layoutHans-Jürgen Rothermel, Dieter A. Mlynski. 37-42 [doi]
• Design automation status in JapanAkihiko Yamada. 43-50 [doi]
• A design automation system for electronic switching systemsT. Hosaka, K. Ueda, H. Matsuura. 51-58 [doi]
• An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita. 59-65 [doi]
• Creating and updating space occupancy and building plans using interactive graphicsR. A. Scoble. 66-73 [doi]
• Plant design management system (PDMS) in action74 [doi]
• Interactive shape generation and spatial conflict testingYehuda E. Kalay. 75-81 [doi]
• Symbolic simulation for functional verification with ADLIB and SDLWendell E. Cory. 82-89 [doi]
• On proving the correctness of optimizing transformations in a digital design automation systemMichael C. McFarland. 90-97 [doi]
• Deterministic systems design from functional specificationsHans Wojtkowiak. 98-104 [doi]
• Hierarchical design verification for large digital systemsTohru Sasaki, Akihiko Yamada, Toshinori Aoyama, Katsutoshi Hasegawa, Shunichi Kato, Shinichi Sato. 105-112 [doi]
• A simulator to replace wire rules for high speed computer designAdrian Hlynka. 113-117 [doi]
• A critical path delay check systemRyotaro Kamikawai, Minoru Yamada, Tsuneyo Chiba, Kenichi Furumaya, Yoji Tsuchiya. 118-123 [doi]
• Survey of analysis, simulation and modeling for large scale logic circuitsAlbert E. Ruehli. 124-129 [doi]
• Routing of printed circuit boardsS. Aranoff, Y. Abulaffio. 130-136 [doi]
• On the use of the linear assignment algorithm in module placementSheldon B. Akers. 137-144 [doi]
• Automatic component placement in an interactive minicomputer environmentCharles F. Shupe. 145-152 [doi]
• PAS-LOP: An automatic module location system for PWBGotaro Odawara, Kazuhiko Iijima, Naoto Ichihara, Tetsuro Kiyomatsu. 153-159 [doi]
• A totally integrated systems approach to design and manufacturing at McDonnell Douglas CorporationMike Mills. 160-165 [doi]
• Mechanical design automation in IBM PoughkeepsieGilbert W. Curl Jr.. 166-170 [doi]
• Application of volumetric modeling to mechanical design and analysisD. L. Dewhirst, R. C. Hillyard. 171-178 [doi]
• A perspective view of the MODCON systemY. K. Chan. 179-188 [doi]
• A maximal resolution guided-probe testing algorithmMiron Abramovici. 189-195 [doi]
• LSI product quality and fault coverageVishwani D. Agrawal, Sharad C. Seth, Prathima Agrawal. 196-203 [doi]
• An algorithmic pretest development for fault identification in analog networksVijay Masurkar. 204-212 [doi]
• Hardware description levels and test for complex circuitsCatherine Bellon, Gabriele Saucier, J. M. Gobbi. 213-219 [doi]
• Automatic generation and characterization of CMOS polycellsC. M. Lee, Basant R. Chawla, S. Just. 220-224 [doi]
• Virtual grid symbolic layoutNeil Weste. 225-233 [doi]
• Combining graphics and a layout language in a single interactive systemStephen Trimberger. 234-239 [doi]
• The Cell Design SystemD. Franco, L. Reed. 240-247 [doi]
• Functional level simulation in FANSIM3 - algorithms, data structures and resultsS. Hirschhorn, M. Hommel, C. Bures. 248-255 [doi]
• Diagnostic system for large scale logic cards and LSI'SSusumu Goshima, Yuichi Oka, Tokinori Kozawa, Teruo Mori, Yoshimitsu Takeguchi, Yasuhiro Ohno. 256-259 [doi]
• PODEM-X: An automatic test generation system for VLSI logic structuresPrabhakar Goel, Barry C. Rosales. 260-268 [doi]
• Digital system simulation: Current status and future trends or darwin's theory of simulationMelvin A. Breuer, Alice C. Parker. 269-275 [doi]
• BOLT-a block oriented design specification languageDan Holt, Steve Sapiro. 276-279 [doi]
• A MOS/LSI oriented logic simulatorDan Holt, Dave Hutchings. 280-287 [doi]
• A timing verification system based on extracted MOS/VLSI circuit parametersPauline Ng, Wolfram Glauert, Robert Kirk. 288-292 [doi]
• An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocksChi-Song Horng, Margaret Lie. 293-300 [doi]
• A State-Machine Synthesizer - SMSDouglas W. Brown. 301-305 [doi]
• Automatic generation of cells for recurrence structuresAvinoam Bilgory, Daniel D. Gajski. 306-313 [doi]
• Overview of an Arithmetic Design SystemDaniel E. Atkins, Wentai Liu, Shauchi Ong. 314-321 [doi]
• ABLE: A LISP-based layout modeling language with user-definable procedural models for storage/logic array designGary B. Goates, Suhas S. Patil. 322-329 [doi]
• Government interest and involvement in design automation development (Panel Discussion)Ronald Waxman, Jonathan Allen, Robert W. Dutton, John M. Gould, Charles W. Gwyn, Paul Losleben, Dan C. Nash, Lawrence Sumney, H. Wayne Spence. 330-331 [doi]
• Government interest and involvement in design automation development (Position paper for the Panel Discussion)Jonathan Allen. 332 [doi]
• Position statement - tools for design automation from a university point of viewRobert W. Dutton. 333 [doi]
• Changing the Government's role in design automation (Position Paper)John M. Gould. 334-335 [doi]
• Government interest and involvement in DA from the Sandia viewpointCharles W. Gwyn. 336 [doi]
• Current issues in government interest and involvement in CADPaul Losleben. 337-341 [doi]
• Government actions to increase CAD software productivityDan C. Nash. 342 [doi]
• Design Automation - a perspective (Position Paper)H. Wayne Spence. 343 [doi]
• Government interest and involvement in design automation development the VHSIC perspectiveLarry W. Sumney. 344-346 [doi]
• Automatic test generation for stuck-open faults in CMOS VLSIYacoub M. El-Ziq. 347-354 [doi]
• Using error latch trace to obtain diagnostic informationPaul M. Almy, Jose L. Rivero. 355-359 [doi]
• Random fault analysisRobert M. McDermott. 360-364 [doi]
• Verification and optimization for LSI & PCB layoutH. Nelson Brady, Robert J. Smith II. 365-371 [doi]
• A high-density multilayer PCB router based on necessary and sufficient conditions for single row routingRaymond Y. Tsui, Robert J. Smith II. 372-381 [doi]
• Performance of interconnection rip-up and reroute strategiesWilliam A. Dees Jr., Robert J. Smith II. 382-390 [doi]
• Automatic PLA synthesis from a DDL-P descriptionSungho Kang, William M. van Cleemput. 391-397 [doi]
• A computer-aided-design system for segmented-folded PLA macro-cellsI. Suwa, William J. Kubitz. 398-405 [doi]
• Optimization of the PLA areaJ.-F. Paillotin. 406-410 [doi]
• Partitioning for VLSI placement problemsArvind M. Patel, L. C. Cote. 411-418 [doi]
• Automatic placement of rectangular blocks with the interconnection channelsR. Malladi, G. Serrero, André Verdillon. 419-425 [doi]
• Placement of variable size circuits on LSI masterslicesK. H. Khokhani, Arvind M. Patel, W. Ferguson, J. Sessa, D. Hatton. 426-434 [doi]
• A set of programs for MOS designG. Sakauye, Anna Lubiw, J. Royle, R. Epplett, Jeffrey Tweedale, E. S. Y. Shew, E. Attfield, Franc Brglez, Philip S. Wilcox. 435-442 [doi]
• PAS-CIP: An interactive logic design systemGotaro Odawara, Satoshi Kurishima, Hiroshi Aoyama, Yasuhiko Kanaya. 443-450 [doi]
• A CAD system for logic design based on frames and demonsTakao Saito, Takao Uehara, Nobuaki Kawato. 451-456 [doi]
• Defining the bounding edges of a SynthaVision solid modelRobert C. Goldstein. 457-461 [doi]
• Geometric modeling technologyWilliam Luts. 462 [doi]
• Interactive graphics for volume modelingRobert N. Wolfe, William J. Fitzgerald, Franklin Gracer. 463-470 [doi]
• The modeling and synthesis of bus systemsChia-Jeng Tseng, Daniel P. Siewiorek. 471-478 [doi]
• A technology relative Logic Synthesis and Module Selection systemG. W. Leive, Donald E. Thomas. 479-485 [doi]
• Algorithms for multiple-criterion design of microprogrammed control hardwareAndrew W. Nagle, Alice C. Parker. 486-493 [doi]
• A multiprocessor raster display for interactive graphics system designWalter M. Anderson. 494-497 [doi]
• A remote design station for customer Uncommitted Logic Array designsFrank R. Ramsay. 498-504 [doi]
• A low cost hierarchical system for VLSI layout and verificationTom H. Edmondson, Richard M. Jennings. 505-510 [doi]
• Process oriented logic simulationSany M. Leinwand. 511-517 [doi]
• GSP: A logic simulator for LSIJames R. Armstrong, D. E. Devlin. 518-524 [doi]
• Vector coding techniques for high speed digital simulationHoward E. Krohn. 525-529 [doi]
• Software engineering applied to computer-aided design (CAD) software developmentDan C. Nash, H. Willman. 530-539 [doi]
• Computer-aided computer-aided design: Improving CAD programmer productivityStanley Wong. 540-545 [doi]
• INCOD: A system for Interactive Conceptual Data Base DesignCarlo Batini, Maurizio Lenzerini. 546-554 [doi]
• An O (N log N) algorithm for Boolean mask operationsUlrich Lauther. 555-562 [doi]
• A concurrent pattern operation algorithm for VLSI mask dataTokinori Kozawa, Akira Tsukizoe, Jun'ya Sakemi, Chihei Miura, Tatsuki Ishii. 563-570 [doi]
• Efficient Boolean operations on IC masksJames A. Wilmore. 571-579 [doi]
• Domain knowledge and the design processJohn McDermott. 580-588 [doi]
• A CODASYL CAD data base systemGünther Zintl. 589-594 [doi]
• A vertically organized computer-aided design data baseKenneth A. Roberts, Thomas E. Baker, David H. Jerome. 595-602 [doi]
• The analog behavior of digital integrated circuitsLance A. Glasser. 603-612 [doi]
• Signal delay in RC tree networksPaul Penfield Jr., Jorge Rubinstein. 613-617 [doi]
• The generation of Technical Data Drawing Packages by the integration of Design Automation GraphicsHarvey N. Lerman. 618-622 [doi]
• User documentation for Design Automation at TIDiana Mae Sims, James Crabbe. 623-631 [doi]
• PRIMEAIDS: An integrated electrical design environmentRoger Cleghorn. 632-638 [doi]
• Automatic input and interactive editing systems of logic circuit diagramsMitsuo Ishii, Yoshikazu Ito, Michiko Iwasaki, Masanari Yamamoto, Sadao Kodama. 639-645 [doi]
• The relational/network Hybrid data model for Design Automation DatabasesMark N. Haynie. 646-652 [doi]
• Data structures for CAD object descriptionMichel Lacroix, Alain Pirotte. 653-659 [doi]
• Some properties of a probabilistic model for global wiringD. Wallace, L. Hemachandra. 660-667 [doi]
• Aiming at a general routing strategyJ. Heinisch. 668-675 [doi]
• Contrasts in physical design between LSI and VLSIWilliam R. Heller. 676-683 [doi]
• Circuit recognition and verification based on layout informationI. Ablasser, U. Jäger. 684-689 [doi]
• PANAMAP-B: A mask verification system for bipolar ICJ. Yoshida, T. Ozaki, Y. Goto. 690-695 [doi]
• Custom VLSI electrical rule checking in an intelligent terminalL. V. Corbin. 696-701 [doi]
• A structured approach to selecting a CAD/CAM systemR. I. McNall Jr., R. J. D'Innocenzo. 702 [doi]
• The "gap" between users and designers of CAD/CAM systems: Search for solutionsJoseph Peled, Michael P. Carroll. 703-705 [doi]
• The role of engineering in the evolving technology/automation interfacePeter E. Barck. 706-707 [doi]
• What to do when the seat of your pants wears out - the formalization of the VLSI design processEd Burdick. 708-709 [doi]
• The effects of CAD on the engineering organization (Position paper)Paul Felton. 710-711 [doi]
• The role of engineering in the evolving technology/automation interfaceR. P. Lydick. 712 [doi]
• Graphics language / one - IBM Corporate-Wide physical design data formatDavid R. Lambert. 713-719 [doi]
• A total verification of printed circuit artworkManfred A. Ward. 720-725 [doi]
• Automatic VLSI layout verificationLaurin Williams. 726-732 [doi]
• An optimum layer assignment for routing in ICs and PCBsMaciej J. Ciesielski, Edwin Kinnen. 733-737 [doi]
• On the layering problem of multilayer PWB wiringShuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa. 738-745 [doi]
• TWIGY - a topological algorithm based routing systemMichel T. Doreau, Piotr Koziol. 746-755 [doi]
• A preprocessor for channel routingMing H. Young, Larry Cooke. 756-761 [doi]
• A dogleg "optimal" channel router with completion enhancementsMichi M. Wada. 762-768 [doi]
• A statistical model for net length estimationLai-Chering Suen. 769-774 [doi]
• A MOS modelling technique for 4-state true-value hierarchical logic simulation or Karnough knowledgeWill Sherwood. 775-785 [doi]
• MOSSIM: A switch-level simulator for MOS LSIRandal E. Bryant. 786-790 [doi]
• Functional modelling for logic simulationPeter G. Raeth, John M. Acken, Gary B. Lamont, John M. Borky. 791-795 [doi]
• AIDE - a tool for computer architecture designD. J. Ellenberger, Ying W. Ng. 796-803 [doi]
• CELTIC - solving the problems of LSI design with an integrated polycell DA systemG. Martin, J. Berrie, T. Little, D. Mackay, J. McVean, D. Tomsett, L. Weston. 804-811 [doi]
• An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3Chiyoji Tanaka, Shinichi Murai, Hiroo Tsuji, Toshihiko Yahara, Kaoru Okazaki, Masayuki Terai, Reiji Katoh, Mikio Tachibana. 812-819 [doi]
• SHARPS: A hierarchical layout system for VLSIToru Chiba, Noboru Okuda, Takashi Kambe, Ikuo Nishioka, Tsuneo Inufushi, Sieji Kimura. 820-827 [doi]
• MILD - A cell-based layout system for MOS-LSIKoji Sato, Takao Nagai, Mikio Tachibana, Hiroyoshi Shimoyama, Masaru Ozaki, Toshihiko Yahara. 828-836 [doi]
• A parallel bit map processor architecture for DA algorithmsTom Blank, Mark Stefik, William M. van Cleemput. 837-845 [doi]
• A formal method for the specification, analysis, and design of register-transfer level digital logicLouis J. Hafer, Alice C. Parker. 846-853 [doi]
• On logic comparisonLeonard Berman. 854-861 [doi]
• Area-time efficient addition in charge based technologyRobert K. Montoye. 862-872 [doi]
• Computer-Aided Design, Manufacturing, Assembly and Test (CADMAT)F. C. Bergsten. 873-880 [doi]
• Test data verification - not just the final step for test data before release for production testingPeter Solecky, R. L. Panko. 881-890 [doi]
• Structured trace diagnosis for LSSD board testing - an alternative to full fault simulated diagnosisFrank C. Hsu, Peter Solecky, Robert E. Beaudoin. 891-897 [doi]