Abstract is missing.
- A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 µm CMOS ProcessDongHyun Ko, Ji-Hoon Jung, YoungGun Pu, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam. 3-6 [doi]
- Compensation-Capacitor Free Pseudo Three-Stage Amplifier with Large Capacitive LoadsKa Nang Leung, Yanqi Zheng. 7-10 [doi]
- The Design and Optimization of a 25 kS/s 10 bit Micropower Current S/H Cell for Weak Current Bio-medical ApplicationsKa Leong Tsang, Jie Yuan. 11-14 [doi]
- A Single-Stage SEPIC PFC Converter for Multiple Lighting LED LampsHsiu-Ming Huang, Shih-Hsiung Twu, Shih-Jen Cheng, Huang-Jen Chiu. 15-19 [doi]
- Using Genetic Evolutionary Software Application Testing to Verify a DSP SoCAdriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Lei. 20-25 [doi]
- Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time ReductionJia Li, Qiang Xu, Yu Hu, Xiaowei Li. 26-31 [doi]
- Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based SystemsClaudia Rusu, Cristian Grecu, Lorena Anghel. 32-37 [doi]
- Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming ApplicationsHans G. Kerkhoff, Jarkko J. M. Huijts. 38-44 [doi]
- A Fast Algorithm for the Chirp Rate EstimationJihai Cao, Ning Zhang, Lin Song. 45-48 [doi]
- Crack Detection on Asphalt Surface Image Using Enhanced Grid Cell AnalysisSiwaporn Sorncharean, Suebskul Phiphobmongkol. 49-54 [doi]
- Interpolation Models for Image Super-resolutionAndrew Gilman, Donald G. Bailey, Stephen Marsland. 55-60 [doi]
- Performance Analysis of a Vehicle Crash Control System using ImageSriram Murali, Ramachandran Shankar. 61-66 [doi]
- A High Speed CMOS Transmitter and Rail-to-Rail ReceiverFeng Zhang, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu. 67-70 [doi]
- Design of a 12-Channel 120-Gbs Optical Receiver Array in 0.18-µm CMOS TechnologyWon-S. Oh, K. Park, J.-C. Choi, C. J. Kim, S. I. Lee, J. K. Moon. 71-74 [doi]
- 99-dB High-Performance Delta-Sigma Modulator for 20-kHz BandwidthYoungkil Choi, Hyungdong Roh, Hyunseok Nam, Jeongjin Roh. 75-78 [doi]
- Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20 MHz Signal Bandwidth, 53.6 dB Dynamic Range and 51.4 dB SNDRTao Wang, Liping Liang. 79-84 [doi]
- An FPGA Implementation of the Searcher AlgorithmA. Sagahyroon, M. El-Tarhuni, S. Ibrahim. 85-88 [doi]
- Analysis of CPU Utilisation and Stack Consumption of a Multimedia Embedded SystemAmith Kumar Nuggehalli Ramachandra, Avin Kumar Kannur. 89-94 [doi]
- Research on System Usability of Digital Libraries in ChinaYaohua Yu, Zhengjie Liu. 95-98 [doi]
- A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC ApplicationJian Ruan, Chung-Len Lee. 99-102 [doi]
- Low Phase Noise Bond Wire VCO for DVB-HKi-Jin Kim, K. H. Ahn, T. H. Lim. 103-106 [doi]
- A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAMMichael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert. 107-110 [doi]
- A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed ApplicationsLiang Shangquan, Gao Minglun, Yin Yongsheng, Deng Honghui. 111-114 [doi]
- A Multiprocessor System for a Small Size Soccer Robot Control SystemCe Li, Yang Jiang, Zhenyu Wu, Takahiro Watanabe. 115-118 [doi]
- Low Cost Arbitration Method for Arbitrarily Scalable Multiprocessor SystemsTero Vallius, Juha Röning. 119-124 [doi]
- An Efficient Design of Single Event Transients Tolerance for Logic CircuitsYantu Mo, Suge Yue. 125-128 [doi]
- Adaptive Diagnostic Pattern Generation for Scan ChainsFei Wang, Yu Hu, Xiaowei Li. 129-132 [doi]
- Built-In Self-Test for Embedded Voltage RegulatorJiang Shi, Ricky Smith. 133-136 [doi]
- Recent Trends in FPGA Architectures and ApplicationsPhilip Heng Wai Leong. 137-141 [doi]
- Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL CompilerFabian Diet, Erik H. D Hollander, Kristof Beyls, Harald Devos. 142-147 [doi]
- Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell ArchitectureZong Wang, Tughrul Arslan, Ahmet T. Erdogan. 148-152 [doi]
- Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPCXun Zhang, Hassan Rabah, Serge Weber. 153-157 [doi]
- xDSL Network Upgrade Employing FPGAsMilos Milosavljevic, Faycal Bensaali, Pandelis Kourtessis. 158-162 [doi]
- Power Issues on Circuit Design for Cochlear ImplantsZhihua Wang, Songping Mai, Chun Zhang. 163-166 [doi]
- Architecture of a Low Storage Digital Pixel Sensor Array with an On-Line Block-Based CompressionMilin Zhang, Amine Bermak. 167-170 [doi]
- Effects of Insulator Thickness on the Sensing Properties of MISiC Schottky-Diode Hydrogen SensorW. M. Tang, C. H. Leung, P. T. Lai. 171-174 [doi]
- High Speed Depth Estimation Using Tilted Focal PlanesHiroshi Ikeoka, Takayuki Hamamoto. 175-178 [doi]
- Multi-Phase Charge Pump Generating Positive and Negative High Voltages for TFT-LCD Gate DrivingChi-Hao Wu. 179-183 [doi]
- Dynamic Co-operative Intelligent MemoryXiaoyong Wen, Faycal Bensaali, Reza Sotudeh. 184-189 [doi]
- An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab MatchingEui-Young Chung, Cheol Hong Kim, Sung Woo Chung. 190-195 [doi]
- Proposal for a Bidirectional Gate Using Pseudo Floating-GateOmid Mirmotahari, Yngvar Berg. 196-200 [doi]
- Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOSBastien Giraud, Amara Amara. 201-204 [doi]
- Compact Models for Signal Transient and Crosstalk Noise of Coupled RLC Interconnect Lines with Ramp InputsTaehoon Kim, Dongchul Kim, Jung-A Lee, Yungseon Eo. 205-209 [doi]
- Improving Diagnosis Resolution without Physical InformationAlexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 210-215 [doi]
- Predictive Die-Level Reliability-Yield Modeling for Deep Sub-micron DevicesMelanie Po-Leen Ooi, Ye Chow Kuang, Chris Chan, Serge N. Demidenko. 216-221 [doi]
- Hierarchical Calculation of Malicious Faults for Evaluating the Fault-ToleranceRaimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee. 222-227 [doi]
- FPGA implementation of a Single Pass Connected Components AlgorithmChristopher T. Johnston, Donald G. Bailey. 228-231 [doi]
- A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering ApplicationsHwang-Cherng Chow, Pu-Nan Weng. 232-235 [doi]
- Workload-Based Dynamic Voltage Scaling with the QoS for Streaming VideoHongmoon Wang, Hyun Suk Choi, Jong-Tae Kim. 236-239 [doi]
- Speech Recognition of Isolated Malayalam Words Using Wavelet Features and Artificial Neural NetworkV. R. Vimal Krishnan, Athulya Jayakumar, Anto P. Babu. 240-243 [doi]
- FPGA Based Real Time Solution for Sensitivity Time ControlD. Meena, L. G. M. Prakasam. 244-248 [doi]
- A Jittered-Sampling Correction Technique for ADCsJamiil Tourabaly, Adam Osseiran. 249-252 [doi]
- Robust JPEG2000 Image Transmission over IEEE 802.15.4Kyu-Yeul Wang, Seung-Yerl Lee, Byung-Soo Kim, Sang-Seol Lee, Jae-Yeon Song, Dong-Sun Kim, Duck Jin Chung. 253-257 [doi]
- New D-Type Flip-Flop Design Using Negative Differential Resistance CircuitsDong-Shong Liang, Kwang-Jow Gan. 258-261 [doi]
- Experimental Characterisations of Coupled Transmission LinesDongchul Kim, Taehoon Kim, Jung-A Lee, Yungseon Eo. 262-265 [doi]
- A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular AutomataBei Cao, Liyi Xiao, Yong-sheng Wang. 266-269 [doi]
- A Test Data Compression Method for System-on-a-ChipJianhua Feng, Guoliang Li. 270-273 [doi]
- A Hybrid of Clonal Selection Algorithm and Frequency Sampling Method for Designing a 2-D FIR FilterTe-Jen Su, Chun-Hsiang Kuo, Wen-Pin Tsai, Cheng-Chih Hou. 274-278 [doi]
- A Generation Flow for Self-Reconfiguration Controllers CustomizationAndrea Cuoccio, Paolo R. Grassi, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. 279-284 [doi]
- Design of High-Speed Floating Point MultiplierSaroja V. Siddamal, R. M. Banakar, B. C. Jinaga. 285-289 [doi]
- High Performance Elliptic Curve Cryptographic Processor Over GF(2^163)Hyun Min Choi, Chun-Pyo Hong, Chang Hoon Kim. 290-295 [doi]
- A Visual Notation for Processor and Resource SchedulingChristopher T. Johnston, Paul Lyons, Donald G. Bailey. 296-301 [doi]
- Design for Testability of Functional Cores in High Performance Node ArchitecturesVenkateswaran Nagarajan, Karthik Chandrasekar, Shrikanth Ganapathy. 302-307 [doi]
- Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree ConstructionYong-Sheng Cheng, Zhi-qiang You, Ji-shun Kuang. 308-313 [doi]
- AES-Based BIST: Self-Test, Test Pattern Generation and Signature AnalysisM. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. 314-321 [doi]
- Oscillation-Based Test in Data Converters: On-Line MonitoringGloria Huertas, José Luis Huertas. 322-325 [doi]
- A Case Study on At-Speed Testing for a Gigahertz MicroprocessorDa Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li. 326-331 [doi]
- A Charge Pump Circuit - Cascading High-Voltage Clock GeneratorWen Chang Huang, Jin Chang Cheng, Po Chih Liou. 332-337 [doi]
- Threshold Voltage Start-up Boost Converter for Sub-mA ApplicationsNgok-Man Sze, Wing-Hung Ki, Chi-Ying Tsui. 338-341 [doi]
- Design of a Low-Voltage CMOS Charge PumpChun Yu Cheng, Ka Nang Leung, Yi Ki Sun, Pui Ying Or. 342-345 [doi]
- High-Input Impedance Voltage-Mode Universal Biquadratic Filter with One input and Five Outputs Using DDCCsWei-Yuan Chiu, Jiun-Wei Horng, Shyuan-Shenq Yang. 346-350 [doi]
- Temporal-Spatial Correlation Based Mode Decision Algorithm for H.264/AVC EncoderBin Zhan, Baochun Hou, Reza Sotudeh. 351-355 [doi]
- A Software-to-Hardware Self-Mapping Technique to Enhance Program Throughput for Portable Multimedia WorkloadsAllen C. Cheng. 356-361 [doi]
- Improved Policies for Drowsy Caches in Embedded ProcessorsJunpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue. 362-367 [doi]
- Improving Cost-Effectiveness Using a Micro-level Static Architecture for Stream ApplicationsPil Woo Chun, Jamin Islam, Valeri Kirischian, Lev Kirischian. 368-373 [doi]
- A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural NetworksXiaoxiao Zhang, Amine Bermak, Farid Boussaïd, Abdesselam Bouzerdoum. 374-377 [doi]
- Temperature Modulation for Tin-Oxide Gas SensorsAicha Far, Bin Guo, Farid Flitti, Amine Bermak. 378-381 [doi]
- Eigenspectra Palmprint RecognitionMoussadek Laadjel, Ahmed Bouridane, Fatih Kurugollu. 382-385 [doi]
- VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream CipherCamel Tanougast, Serge Weber, Gilles Millerioux, Jamal Daafouz, Ahmed Bouridane. 386-389 [doi]
- DWT/PCA Face Recognition using Automatic Coefficient SelectionPaul Nicholl, Abbes Amira. 390-393 [doi]
- A Spiking Neural Network for Gas Discrimination Using a Tin Oxide Sensor ArrayMaxime Ambard, Bin Guo, Dominique Martinez, Amine Bermak. 394-397 [doi]
- A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable ComputingThomas Lenart, Henrik Svensson, Viktor Öwall. 398-404 [doi]
- A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design FlowAlessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. 405-409 [doi]
- High-Speed Priority Queue Architecture for Multiple Out LinksSang-Gyun Kim, Woo-Sik Kim, Seung Ho Ok, Byung-In Moon. 410-414 [doi]
- Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip ArchitecturesHsin-Chou Chi, Chia-Ming Wu, Jun-Hui Lee. 415-420 [doi]
- Drift Invariant Gas Recognition Technique for On Chip Tin Oxide Gas Sensor ArrayFarid Flitti, Aicha Far, Bin Guo, Amine Bermak. 421-424 [doi]
- On Using Fingerprint-Sensors for PIN-Pad EntryMarcel Jacomet, Josef Goette, Andreas Eicher. 425-430 [doi]
- FPGA Implementation of a Predictive Vector Quantization Image Compression Algorithm for Image Sensor ApplicationsYan Wang, Amine Bermak, Abdesselam Bouzerdoum, Brian W. Ng. 431-434 [doi]
- Integrating Dynamic Load Balancing Strategies into the Car-NetworkIsabell Jahnich, Ina Podolski, Achim Rettberg. 435-440 [doi]
- A Design of the Frequency Synthesizer for UWB Application in 0.13 µm RF CMOS ProcessJinKyung Kim, Sung-Kyu Jung, Ji-Hoon Jung, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam, Bong-Hyuk Park, Sang-Sung Choi. 441-445 [doi]
- Analog to Digital Converter Specification for UMTS/FDD Receiver ApplicationsZulhakimi Razak, Tughrul Arslan. 446-449 [doi]
- A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable SystemsAlessio Montone, Marco D. Santambrogio, Donatella Sciuto. 450-453 [doi]
- Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level SynthesisHariharan Sankaran, Srinivas Katkoori. 454-457 [doi]
- Scalable Montgomery Multiplier for Finite Fields GF(p) and GF(2^m)Tae-Ho Kim, Sang-Chul Kim, Chang Hoon Kim, Chun-Pyo Hong. 458-461 [doi]
- Static Crosstalk Noise Analysis with Transition MapMinjin Zhang, Huawei Li, Xiaowei Li. 462-465 [doi]
- Implementation of the Embedded System for Visually-Impaired PeopleSi-Woo Kim, Jae-Kyun Lee, Boo-Shik Ryu, Chae-Wook Lee. 466-469 [doi]
- Model-Based Gaze Direction Estimation in Office EnvironmentDo Joon Jung, Kyung Su Kwon, Se Hyun Park, Jong Bae Kim, Hang Joon Kim. 470-473 [doi]
- Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGAStefan Lachowicz, Hans-Jörg Pfleiderer. 474-477 [doi]
- Configurable Blocks for Multi-precision MultiplicationOliver A. Pfänder, Reinhard Nopper, Hans-Jörg Pfleiderer, Shun Zhou, Amine Bermak. 478-481 [doi]
- High Performance FPGA Implementation of the Mersenne TwisterShrutisagar Chandrasekaran, Abbes Amira. 482-485 [doi]
- Addressing Heterogeneous Bandwidth Requirements in Modified Fat-Tree Networks-on-ChipsA. Bouhraoua, M. E. Elrabaa. 486-490 [doi]
- The Fourier Spectrum Analysis of Optical Feedback Self-Mixing Signal under Weak and Moderate FeedbackXiaojun Zhang, Jiangtao Xi, Yanguang Yu, Joe Chichero. 491-495 [doi]
- Elimination of Gamma Non-linear Luminance Effects for Digital Video Projection Phase Measuring ProfilometersMatthew J. Baker, Jingtai Xi, Joe F. Chicharo. 496-501 [doi]
- Integrated CMOS Analog Neural Network Ability to Linearize the Distorted Characteristic of HPA Embedded in SatellitesLaurent Gatet, Hélène Tap-Béteille, Daniel Roviras, Francis Gizard. 502-505 [doi]
- Compact Gray-Code Counter/Memory Circuits for Spiking PixelsKwan Ting Ng, Chen Shoushun, Farid Boussaïd, Amine Bermak. 506-511 [doi]
- Calibration and Debugging of Multi-step Analog to Digital ConvertersAmir Zjajo, José Pineda de Gyvez. 512-515 [doi]
- A Prevenient Voltage Stress Test Method for High Density MemoryJongsoo Yim, Gunbae Kim, Incheol Nam, Sangki Son, Jonghyoung Lim, Hwacheol Lee, Sangseok Kang, Byungheon Kwak, Jinseok Lee, Sungho Kang. 516-520 [doi]
- A Scan-Based Delay Test Method for Reduction of OvertestingHui Liu, Huawei Li, Yu Hu, Xiaowei Li. 521-526 [doi]
- An Integrated Validation Environment for Differential Power AnalysisGiorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 527-532 [doi]
- Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive NetworksPaul Milbredt, Andreas Steininger, Martin Horauer. 533-538 [doi]
- Early Design Phase Power Performance Trade-Offs Using In-Situ Macro ModelsCharles Thangaraj, Tom Chen. 539-544 [doi]
- Low Voltage Design against Power Analysis AttacksOmid Mirmotahari, Yngvar Berg. 545-548 [doi]
- Electrical Power Monitoring System Using Thermochron Sensor and 1-Wire Communication ProtocolMoi-Tin Chew, Tatt-Huong Tham, Ye Chow Kuang. 549-554 [doi]
- Efficient VLSI Layout of Edge Product NetworksSaeedeh Bakhshi, Hamid Sarbazi-Azad. 555-560 [doi]
- Towards a Petri Net Based Approach to Model and Synthesise Dynamic Reconfiguration for FPGAsHelene Schilke, Achim Rettberg, Florian Dittmann. 561-566 [doi]
- Arbitrary Waveform Generator Based on Direct Digital Frequency SynthesizerWeibo Hu, Chung-Len Lee, Xin an Wang. 567-570 [doi]
- Design of a Data Concentrator Card for the Readout of the Compact Muon Solenoid Electromagnetic CalorimeterJose Carlos Da Silva, Michal Hujesko, Joao Varela. 571-575 [doi]
- A Novel Approach to High-Level Property Checking Using Wu s MethodZhi Yang, Guangsheng Ma, Shu Zhang. 576-580 [doi]
- Test Set Stripping Limiting the Maximum Number of Specified BitsMichael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Hans-Joachim Wunderlich. 581-586 [doi]
- An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified SamplingWeiguang Sheng, Liyi Xiao, Zhigang Mao. 587-591 [doi]
- CreaTe: A New Programme to Attract Engineers as Design ArtistsZsófia Ruttkay, Ton J. Mouthaan. 592-596 [doi]
- High-Performance Pseudorandom Number Generator Using Two-Dimensional Cellular AutomataByung-Heon Kang, Dong-Ho Lee, Chun-Pyo Hong. 597-602 [doi]
- Design Automation of UHF RFID Tag Antenna Design Using a Genetic Algorithm Linked to MWS CSTKyounghwan Lee, YoungJu Kim, You Chung Chung. 603-606 [doi]