Table of Contents

• Advanced Fault-Tolerance Techniques for a Color Digital Camera-on-a-ChipIsrael Koren, Zahava Koren, Glenn H. Chapman. 3-10 [doi]
• Challenges Facing Practical DFT for MEMSS. K. Tewksbury. 11-17 [doi]
• Design of a Self-Correcting Active Pixel SensorYves Audet, Glenn H. Chapman. 18 [doi]
• Yield-Reliability Modeling for Fault Tolerant Integrated CircuitsThomas S. Barnett, Adit D. Singh, Victor P. Nelson. 29-38 [doi]
• A Simple via Duplication Tool for Yield EnhancementNeil Harrison. 39-47 [doi]
• Relation between Reliability and Yield of IC s Based on Discrete Defect Distribution ModelTianxu Zhao, Yue Hao, Peijun Ma, Taifeng Chen. 48 [doi]
• An On-Chip Detection Circuit for the Verification of IC Supply ConnectionsHans A. R. Manhaeve, Stefaan Kerckenaere. 57-65 [doi]
• On-Line Error Detectable Carry-Free Adder DesignParag K. Lala, Alvernon Walker. 66-71 [doi]
• Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number SystemShugang Wei, Kensuke Shimizu. 72-77 [doi]
• Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating LogicTat Ngai, Earl E. Swartzlander Jr., Chen He. 78-83 [doi]
• High Level Modifications of VHDL Descriptions for On-Line Test or Fault ToleranceRégis Leveugle, R. Cercueil. 84 [doi]
• Embedded Core Testing Using Broadcast Test ArchitectureJ. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone. 95-103 [doi]
• Analyzing BIST RobustnessJanusz Sosnowski. 104-109 [doi]
• Test Pattern Decompression Using a Scan ChainOndrej Novák, Jiri Nosek. 110-115 [doi]
• Reducing Power Dissipation during At-Speed Test ApplicationXiaowei Li, Huawei Li, Yinghua Min. 116 [doi]
• Permanent Fault Repair for FPGAs with Limited Redundant AreaShu-Yi Yu, Edward J. McCluskey. 125-133 [doi]
• Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare ReplacementItsuo Takanami. 134-142 [doi]
• ABL-Tree: A Constant Diameter Interconnection Network for Reconfigurable Processor Arrays Capable of Distributed Communication Nobuo Tsuda. 143-148 [doi]
• On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router John M. Emmert, Jason A. Cheatham. 149 [doi]
• Novel Approaches for Fault Detection in Two-Dimensional Combinational ArraysXiao-Tao Chen, Wei-Kang Huang, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi. 161-169 [doi]
• A Software Methodology for Detecting Hardware Faults in VLIW Data PathsCristiana Bolchini, Fabio Salice. 170-175 [doi]
• Efficient Parity Prediction in FPGASeok-Bum Ko, Tian Xia, Jien-Chung Lo. 176-181 [doi]
• Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection LatencyNahmsuk Oh, Edward J. McCluskey. 182 [doi]
• A Fault-Tolerance Strategy for an FPGA-Based Multi-stage Interconnection Network in a Multi-sensor System for Space ApplicationMonica Alderighi, Fabio Casini, Sergio D Angelo, Davide Salvi, Giacomo R. Sechi. 191-199 [doi]
• Idle Cycles Based Concurrent Error Detection of RC6 EncryptionKaijie Wu, Ramesh Karri. 200-205 [doi]
• Fast Run-Time Fault Location in Dependable FPGA-Based ApplicationsWei-Je Huang, Subhasish Mitra, Edward J. McCluskey. 206-214 [doi]
• Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting ReconfigurabilityJayabrata Ghosh-Dastidar, Nur A. Touba. 215-220 [doi]
• Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic ModulesXiaoling Sun, Jian Xu, Pieter M. Trouborst. 221 [doi]
• Comparison and Application of Different VHDL-Based Fault Injection TechniquesJoaquin Gracia, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil. 233-241 [doi]
• A Low-Cost Hardware Approach to Dependability Validation of IpsRégis Leveugle. 242-249 [doi]
• Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 250-258 [doi]
• Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary ResultsRaoul Velazco, Régis Leveugle, O. Calvo. 259 [doi]
• Parallel Testing of Multi-port Static Random Access Memories for BISTFarzin Karimi, Fabrizio Lombardi. 271-279 [doi]
• A Speed-Dependent Approach for Delta IDDQ ImplementationPaul Lee, Alfred Chen, Dilip Mathew. 280-286 [doi]
• Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric FieldHiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada. 287 [doi]
• Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting CapabilitiesKazuteru Namba, Eiji Fujiwara. 299-307 [doi]
• Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-Error-Correcting Codes for On-Chip DRAM ApplicationsAmir Kazéminéjad, Eric Belhaire. 308-313 [doi]
• Design of Fault-Secure Encoders for a Class of Systematic Error Correcting CodesStanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro. 314 [doi]
• Sensitivity and Reliability Evaluation for Mixed-Signal ICs under Electromigration and Hot-Carrier EffectsXiangdong Xuan, Abhijit Chatterjee. 323-328 [doi]
• A Step Response Based Mixed-Signal BIST Approach Alvernon Walker. 329-337 [doi]
• Analog BIST Generator for ADC TestingSerge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell. 338-346 [doi]
• Reliability Enhancement of Analog-to-Digital Converters (ADCs)Mandeep Singh, Israel Koren. 347 [doi]
• Evaluation of Clock Distribution Networks Most Likely Faults and Produced EffectsCecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak. 357-365 [doi]
• Defect Analysis and a New Fault Model for Multi-port SRAMsPradeep Nagaraj, Shambhu Upadhaya, Kamran Zarrineh, R. Dean Adams. 366-374 [doi]
• Development of the Special Software Tools for the Defect/Fault Analysis in the Complex Gates from Standard Cell LibraryMykola Blyzniuk, Irena Kazymyra. 375-383 [doi]
• CMOS Standard Cells Characterization for Defect Based TestingWitold A. Pleskacz, Dominik Kasprowicz, Tomasz Oleszczak, Wieslaw Kuzmicz. 384 [doi]
• Survivable Self-Checking Sequential CircuitsA. Matrosova, Sergey Ostanin, Ilya Levin. 395-402 [doi]
• Design of a Totally Self Checking Signature Analysis Checker for Finite State MachinesMarco Ottavi, Gian-Carlo Cardarilli, D. Cellitti, Salvatore Pontarelli, Marco Re, Adelio Salsano. 403-411 [doi]
• Fail-Safe Synchronization Circuit for Duplicated SystemsEleftherios Kolonis, Michael Nicolaidis. 412-417 [doi]
• How to Tune the MTTF of a Fail-Silent SystemAndreas Steininger, Christoph Scherrer. 418 [doi]
• Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher ArchitectureRamesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim. 427-435 [doi]
• On Variable-Shift-Based Fault Compensation of Fuzzy ControllersNaotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui. 436-444 [doi]
• On-Line Fault Tolerance for FPGA Interconnect with Roving STARsJohn M. Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici. 445-454 [doi]
• System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation MethodologySalvatore Pontarelli, Gian-Carlo Cardarilli, A. Malvoni, Marco Ottavi, Marco Re, Adelio Salsano. 455-460 [doi]
• Performance Evaluation of Checksum-Based ABFTAhmad A. Al-Yamani, Nahmsuk Oh, Edward J. McCluskey. 461 [doi]