Abstract is missing.
- The Future of Test - Product Integration and its Impact on TestMichael Campbell. 3 [doi]
- Low DPM: Why Do We Need it and What Does it Cost!Sandeep P. Kumar. 7 [doi]
- Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and SystemsGeorge J. Starr, Jie Qin, Bradley F. Dutton, Charles E. Stroud, Foster F. Dai, Victor P. Nelson. 11-19 [doi]
- Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control PointsJoon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba. 20-28 [doi]
- Soft Core Embedded Processor Based Built-In Self-Test of FPGAsBradley F. Dutton, Charles E. Stroud. 29-37 [doi]
- On-chip Generation of the Second Primary Input Vectors of Broadside TestsIrith Pomeranz, Sudhakar M. Reddy. 38-46 [doi]
- Flip-Flop Hardening and Selection for Soft Error and Delay Fault ResilienceMingjing Chen, Alex Orailoglu. 49-57 [doi]
- A Novel Hardened Design of a CMOS Memory Cell at 32nmSheng Lin, Yong-Bin Kim, Fabrizio Lombardi. 58-64 [doi]
- Novel High Speed Robust LatchMartin Omaña, Daniele Rossi, Cecilia Metra. 65-73 [doi]
- Are Robust Circuits Really Robust?Sybille Hellebrand, Marc Hunger. 77-77 [doi]
- Challenges in Delay Testing of Integrated CircuitsD. M. H. Walker. 81-82 [doi]
- Using RRNS Codes for Cluster Faults Tolerance in Hybrid MemoriesNor Zaidi Haron, Said Hamdioui. 85-93 [doi]
- Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and PowerAaron Dingler, M. Jafar Siddiq, Michael T. Niemier, Xiaobo Sharon Hu, M. Tanvir Alam, Gary H. Bernstein, Wolfgang Porod. 94-102 [doi]
- Coded DNA Self-Assembly for Error Detection/LocationZahra Mashreghian Arani, Masoud Hashempour, Fabrizio Lombardi. 103-111 [doi]
- Errors in DNA Self-Assembly by Synthesized Tile SetsXiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabrizio Lombardi. 112-120 [doi]
- Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICsNaveed A. Sherwani. 123-123 [doi]
- Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable SensorsMartin Omaña, Marcin Marzencki, Roberto Specchia, Cecilia Metra, Bozena Kaminska. 127-135 [doi]
- SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000Shih-Hsin Hu, Tung-Yeh Wu, Jacob A. Abraham. 136-144 [doi]
- Reduced Precision Checking for a Floating Point AdderPatrick J. Eibl, Andrew D. Cook, Daniel J. Sorin. 145-152 [doi]
- Characterization of Gain Enhanced In-Field Defects in Digital ImagersJenny Leung, Glenn H. Chapman, Israel Koren, Zahava Koren. 155-163 [doi]
- Analysis of Resistive Open Defects in a SynchronizerHyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang. 164-172 [doi]
- A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA SystemsCristiana Bolchini, Fabrizio Castro, Antonio Miele. 173-181 [doi]
- On the Functional Qualification of a Platform ModelGiuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Mark Hampton, Florian Letombe. 182-190 [doi]
- A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS CircuitsDavid Wolpert, Paul Ampadu. 193-201 [doi]
- A Reconfigurable ADC Circuit with Online-Testing Capability and Enhanced Fault ToleranceYueran Gao, Haibo Wang. 202-210 [doi]
- Improving Memory Repair by Selective Row PartitioningMuhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba. 211-219 [doi]
- Software-Based Hardware Fault Tolerance for Many-Core ArchitecturesHans-Joachim Wunderlich. 223-223 [doi]
- Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?Marcelo Lubaszewski. 224-224 [doi]
- Testing of Switch Blocks in Three-Dimensional FPGATakumi Hoshi, Kazuteru Namba, Hideo Ito. 227-235 [doi]
- A Study of Side-Channel Effects in Reliability-Enhancing TechniquesJianwei Dai, Lei Wang. 236-244 [doi]
- Reliability and Performance Analysis of FPGA-Based Fault Tolerant SystemRyoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue. 245-253 [doi]
- An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAsMatteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis. 254-262 [doi]
- Minimizing Observation Points for Fault LocationSnehal Udar, Dimitri Kagaris. 263-267 [doi]
- Optimizing Parametric BIST Using Bio-inspired Computing AlgorithmsNastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi. 268-276 [doi]
- Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance MechanismsMeng Zhang, Anita Lungu, Daniel J. Sorin. 277-285 [doi]
- System Level Testing via TLM 2.0 Debug Transport InterfaceStefano Di Carlo, Nadereh Hatami, Paolo Prinetto, Alessandro Savino. 286-294 [doi]
- Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus FragmentsNader Alawadhi, Ozgur Sinanoglu. 295-303 [doi]
- Transient Error Detection and Recovery in Processor PipelinesSyed Zafar Shazli, Mehdi Baradaran Tahoori. 304-312 [doi]
- Fault-Tolerant Routing Algorithm for Network on Chip without Virtual ChannelsYusuke Fukushima, Masaru Fukushi, Susumu Horiguchi. 313-321 [doi]
- Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield AnalysisYehua Su, Wenjing Rao. 322-330 [doi]
- Complementary Formal Approaches for Dependability AnalysisSouheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud. 331-339 [doi]
- Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR)Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici. 340-348 [doi]
- An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer LevelYu Liu, Kaijie Wu. 349-357 [doi]
- Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test SequencesIrith Pomeranz, Sudhakar M. Reddy. 358-366 [doi]
- Error Control Coding for Multilevel Cell Flash Memories Using Nonbinary Low-Density Parity-Check CodesYuu Maeda, Haruhiko Kaneko. 367-375 [doi]
- Resilience Challenges for Exascale SystemsNorman P. Jouppi. 379-379 [doi]
- Improving the Detectability of Resistive Open Faults in Scan CellsFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz. 383-391 [doi]
- An Incremental Approach to Functional DiagnosisLuca Amati, Cristiana Bolchini, Laura Frigerio, Fabio Salice, William Eklow, Arnold Suvatne, Eugenio Brambilla, Federico Franzoso, Michele Martin. 392-400 [doi]
- Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone PartitioningStelios Neophytou, Maria K. Michael, Kyriakos Christou. 401-409 [doi]
- Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-ChipUnni Chandran, Dan Zhao. 410-418 [doi]
- Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern MicroprocessorsYiorgos Makris. 421-421 [doi]
- A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOSAdit D. Singh. 422-422 [doi]
- Error Correction Codes for SEU and SEFI Tolerant Memory SystemsSalvatore Pontarelli, Gian-Carlo Cardarilli, Marco Re, Adelio Salsano. 425-430 [doi]
- Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-ChipQiaoyan Yu, Paul Ampadu. 431-439 [doi]
- Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip InterconnectsBo Fu, Paul Ampadu. 440-448 [doi]
- Data Learning Techniques for Functional/System Fmax PredictionLi-C. Wang. 451-451 [doi]