Abstract is missing.
- The Challenges for High Performance Embedded SystemsMarc Duranton. 3-7 [doi]
- Digital RFRoman Staszewski. 8 [doi]
- Deep Sub-100 nm Design ChallengesTohru Furuyama. 9-16 [doi]
- New Directions in Mobile Device ArchitecturesRisto Suoranta. 17-26 [doi]
- Robustness in SOC DesignKlaus Waldschmidt. 27-36 [doi]
- Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC CommunicationZhonghai Lu, Ingo Sander, Axel Jantsch. 37-44 [doi]
- Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip CommunicationSander Stuijk, Twan Basten, Marc Geilen, Amir Hossein Ghamarian, Bart D. Theelen. 45-52 [doi]
- On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC ArchitecturesFrédéric Pétrot, Alain Greiner, Pascal Gomez. 53-60 [doi]
- Partition Based Dynamic 2D HW Multitasking ManagementSara Román Navarro, Hortensia Mecha, Daniel Mozos, Julio Septién. 61-70 [doi]
- Global Analysis of Resource Arbitration for MPSoCAkash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha. 71-78 [doi]
- Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop FilteringAlokika Dash, Peter Petrov. 79-82 [doi]
- Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGAAri Kulmala, Timo D. Hämäläinen, Marko Hännikäinen. 83-88 [doi]
- Multi-Bank Main Memory Architecture with Dynamic Voltage Frequency Scaling for System Energy OptimizationHanene Ben Fradj, Cécile Belleudy, Michel Auguin. 89-96 [doi]
- A Monitoring-Aware Network-on-Chip Design FlowCalin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten. 97-106 [doi]
- A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image ProcessingReid B. Porter, Jan R. Frigo, Maya Gokhale, Christophe Wolinski, François Charot, Charles Wagner. 107-115 [doi]
- A Hardware IP-Core for Information RetrievalMichael Freeman, Thimal Jayasooriya. 115-122 [doi]
- Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal ProblemsKyriakos Stavrou, Pedro Trancoso. 123-126 [doi]
- Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processorsMichael Freeman. 127-130 [doi]
- Solving the Fundamental Problem of Digital Design - A Systematic Review of Design MethodsMartin Delvai, Andreas Steininger. 131-138 [doi]
- Dependable Design for FPGA Based on Duplex System and ReconfigurationPavel Kubalík, Radek Dobias, Hana Kubatova. 139-145 [doi]
- A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA BlocksLucia Bissi, Pisana Placidi, Giuseppe Baruffa, Andrea Scorzoni. 146-154 [doi]
- An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n)Ramachandruni Venkata Kamala, M. Sudhakar, M. B. Srinivas. 155-159 [doi]
- Application Specific Instruction Set Processor for Adaptive Video Motion EstimationSvetislav Momcilovic, Tiago Dias, Nuno Roma, Leonel Sousa. 160-167 [doi]
- Novel Modulo 2:::n::: + 1 MultipliersHaridimos T. Vergos, Costas Efstathiou. 168-175 [doi]
- Embedded Parallel Systems Based on Dynamic Look-Ahead Reconfiguration in Redundant Communication ResourcesEryk Laskowski, Marek Tudruj. 176-179 [doi]
- BCB: A Buffered CrossBar Switch Fabric Utilizing Shared MemoryGeorge Kornaros. 180-188 [doi]
- Design and Application of a Scalable Embedded Systems Architecture with an FPGA Based Operating InfrastuctureFritz Mayer-Lindenberg. 189-196 [doi]
- Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication BasisSylvain Collange, Jérémie Detrey, Florent de Dinechin. 197-203 [doi]
- Adapting EPIC Architecture s Register Stack for Virtual Stack MachinesJamel Tayeb, Smaïl Niar. 204-210 [doi]
- Dual-Mode Quadruple Precision Floating-Point AdderAhmet Akkas. 211-220 [doi]
- Adaptive High-End Microprocessor for Power-Performance EfficiencyPedro Trancoso. 221-228 [doi]
- Profiling Bluetooth and Linux on the Xilinx Virtex II ProFilipa Duarte, Stephan Wong. 229-235 [doi]
- A Linear Convergent Functional Iterative DivisionWithout a Look-Up TableViay Holimath, Javier D. Bruguera. 236-239 [doi]
- A Computation Core for Communication Refinement of Digital Signal Processing AlgorithmsSylvain Huet, Emmanuel Casseau, Olivier Pasquier. 240-250 [doi]
- Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HWMartin Stáva, Ondrej Novák. 251-256 [doi]
- An Asynchronous PLA with Improved Security CharacteristicsPetros Oikonomakos, Simon W. Moore. 257-264 [doi]
- Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level InformationGiovanni Busonera, Salvatore Carta, Andrea Marongiu, Luigi Raffo. 265-268 [doi]
- A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded SystemsRoberto R. Osorio, Javier D. Bruguera. 269-274 [doi]
- A Mixed Language Fault Simulation of VHDL and SystemCSilvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber. 275-279 [doi]
- FPGA Implementation of Embedded Cruise Control and Anti-Collision RadarSébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser. 280-287 [doi]
- A Flexible, Syntax Independent Representation (SIR) for System Level Design ModelsInes Viskic, Rainer Dömer. 288-294 [doi]
- Prototyping Parallel FDTD Programs by Macro Data Flow Graph AnalysisAdam Smyk, Marek Tudruj. 295-304 [doi]
- VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and SystemsArmando Sánchez-Peña, Pedro P. Carballo, Luz García, Antonio Núñez. 305-312 [doi]
- Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng. 313-322 [doi]
- Transition Fault Test ReuseEduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas. 323-330 [doi]
- Abstract Application Modeling for System Design Space ExplorationMuhammad Waseem, Ludovic Apvrille, Rabéa Ameur-Boulifa, Sophie Coudert, Renaud Pacalet. 331-337 [doi]
- Characterization of the EMC Performances of the CAN Bus in a Typical System Bus Architecture for Small SatellitesGianluca Casarosa, Michele Apuzzo, Luca Fanucci, Bruno Sarti. 338-345 [doi]
- Utilising Evolutionary Approaches and Object Oriented Techniques for Design Space ExplorationLiam Noonan, Colin Flanagan. 346-352 [doi]
- High-Level Decision Diagram based Fault Models for Targeting FSMsJaan Raik, Raimund Ubar, Taavi Viilukas. 353-358 [doi]
- Cascade Scheme for Concurrent Errors DetectionIlya Levin, Vladimir Ostrovsky, Osnat Keren, Vladimir Sinelnikov. 359-368 [doi]
- Flexible Two-Level Boolean Minimizer BOOM-II and Its ApplicationsPetr Fiser, Hana Kubatova. 369-376 [doi]
- DRedSOP: Synthesis of a New Class of Regular FunctionsAnna Bernasconi, Valentina Ciriani. 377-384 [doi]
- Multi-objective Optimal FSM State AssignmentLech Józwiak, Aleksander Slusarczyk, Dominik Gawlowski. 385-396 [doi]
- Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCsLech Józwiak, Sien-An Ong. 397-406 [doi]
- A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost QuantizationJavier D. Bruguera, Roberto R. Osorio. 407-414 [doi]
- Rachael SPARC: An Open Source 32-bit Microprocessor Core for SoCsMichael Cowell, Adam Postula. 415-422 [doi]
- Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous CounterpartJosé Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López. 423-432 [doi]
- Scan-Based SoC Test Using Space / Time Pattern Compaction SchemesChristian Galke, U. Gätzschmann, Heinrich Theodor Vierhaus. 433-438 [doi]
- Hardware-Software Codesign of a Vector Co-processor for Public Key CryptographyJacques J. A. Fournier, Simon W. Moore. 439-446 [doi]
- Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB StandardArjan C. Dam, Michel G. J. Lammertink, Kenneth C. Rovers, Johan Slagman, Arno M. Wellink. 447-455 [doi]
- A Power-Aware Technique for Functional Units in High-Performance ProcessorsGuadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar. 456-459 [doi]
- Automata Construct with Genetic AlgorithmVít Fábera, Vlastimil Jánes, Mária Jánesová. 460-463 [doi]
- ATOMI II - Framework for Easy Building of Object-oriented Embedded SystemsTero Vallius, Juha Röning. 464-474 [doi]
- A RISC Processor with Redundant LNS InstructionsMark G. Arnold. 475-482 [doi]
- State Assignment for Detecting Erroneous Transitions in Finite State MachinesMarkus Damm. 483-490 [doi]
- Memory Generation and Power Distribution In SOCQing K. Zhu. 491-495 [doi]
- A Graph Based Algorithm for Data Path Optimization in Custom ProcessorsJelena Trajkovic, Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski. 496-503 [doi]
- Testability Estimation Based on Controllability and Observability ParametersTomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina. 504-514 [doi]
- Performance Improvement for H.264 Video Encoding using ILP Embedded ProcessorAli R. Iranpour, Krzysztof Kuchcinski. 515-521 [doi]
- Function Call Optimization in Behavioral SynthesisYuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada. 522-529 [doi]
- Design Guides for a Correct DC Operation in RTD-based Threshold GatesJosé M. Quintana, Maria J. Avedillo, Juan Núñez. 530-536 [doi]
- Layered Decoding of Non-Layered LDPC CodesMassimo Rovini, Francesco Rossi, Pasquale Ciao, Nicola L Insalat, Luca Fanucci. 537-544 [doi]
- Design and Validation of Digital Channels for a Galileo Receiver PrototypeFrancesco Rossi, Massimo Rovini, Luca Fanucci. 545-549 [doi]
- Two Architectures of a General Digit-Serial Normal Basis MultiplierMartin Novotný, Jan Schmidt. 550-553 [doi]
- An Embedded Architecture for Mission Control of Unmanned Aerial VehiclesE. Pastor, J. Lopez, P. Royo. 554-560 [doi]
- Design of a Low-Power Digital Core for Passive UHF RFID TransponderAndrea Ricci, Matteo Grisanti, Ilaria De Munari, Paolo Ciampolini. 561-568 [doi]
- A Portable System for Measuring Human Body MovementG. M. Bertolotti, A. Cristiani, R. Gandolfi, R. Lombardi. 569-576 [doi]
- Design and Implementation of Low-Area and Low-Power AES Encryption Hardware CorePanu Hämäläinen, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen. 577-583 [doi]
- Clock-Gating in FPGAs: A Novel and Comparative EvaluationYan Zhang, Jussi Roivainen, Aarne Mämmelä. 584-590 [doi]
- Improving Delivery Ratio and Power Efficiency in Unicast Geographic Routing with a Realistic Physical Layer for Wireless Sensor NetworksJuan A. Sánchez, Pedro M. Ruiz. 591-597 [doi]
- Opportunistic Pervasive Computing with Domain-Oriented Virtual MachinesJaroslaw Domaszewicz, Michal Rój, A. Pruszkowski. 598-605 [doi]
- Lifetime Analysis in Heterogeneous Sensor NetworksFalko Dressler, Isabel Dietrich. 606-616 [doi]
- Wireless Medical Information System Network for Patient ECG MonitoringMatthew D Souza, Montserrat Ros, Adam Postula. 617-624 [doi]
- Voltage Sensors for Supply Capacitor in Passive UHF RFID TranspondersR. Morales-Ramos, Juan A. Montiel-Nelson, R. Berenguer, A. Garcia-Alonso. 625-629 [doi]
- Improved Precision of Coarse Grained Localization in Wireless Sensor NetworksFrank Reichenbach, Jan Blumenthal, Dirk Timmermann. 630-640 [doi]
- A Simple Clockless Network-on-Chip for a Commercial Audio DSP ChipMikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen. 641-648 [doi]
- Adaptive Power Management for the On-Chip Communication NetworkGuang Liang, Axel Jantsch. 649-656 [doi]
- Packetizing OCP Transactions in the MANGO Network-on-ChipTobias Bjerregaard, Jens Sparsø. 657-664 [doi]
- Designing Efficient Irregular Networks for Heterogeneous Systems-on-ChipChristian Neeb, Norbert Wehn. 665-672 [doi]
- A High Level Power Model for the Nostrum NoCSandro Penolazzi, Axel Jantsch. 673-676 [doi]
- Off-Line Testing of Delay Faults in NoC InterconnectsTomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng. 677-680 [doi]
- Flexible Bus and NoC Performance Analysis with Configurable Synthetic WorkloadsRikard Thid, Ingo Sander, Axel Jantsch. 681-688 [doi]
- Energy Reduction through Crosstalk Avoidance Coding in NoC ParadigmPartha Pratim Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu. 689-695 [doi]
- Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with RegionsRickard Holsmark, Maurizio Palesi, Shashi Kumar. 696-703 [doi]