Table of Contents

• An extendible design exploration tool for supporting approximate computing techniquesMario Barbareschi, Federico Iannucci, Antonino Mazzeo. 1-6 [doi]
• Simple tri-state logic Trojans able to upset properties of ring oscillatorsLeonel Acunha Guimaraes, Rodrigo Possamai Bastos, Thiago Ferreira de Paiva Leite, Laurent Fesquet. 1-6 [doi]
• Lowpass filter design technique for hybrid and monolithic implementationFaycal Amrani, Mohamed Trabelsi, Abdelhalim A. Saadi, Rachida Touhami. 1-4 [doi]
• Fused modulo 2n + 1 add-multiply unit for weighted operandsKiamal Z. Pekmestzi, Kostas Tsoumanis, Constantinos Efstathiou. 1-6 [doi]
• A discrete implementation of a bidirectional circuit for actuation and read-out of resonating sensorsLuca Marchetti, Amar Romi, Yngvar Berg, Omid Mirmotahari, Mehdi Azadmehr. 1-5 [doi]
• Analytical optimization of interdigitated structure for biological medium characterizationM. Dekmous, A. Lakhdari, H. Mouhadjer, N. Mekkakia-Maaza. 1-4 [doi]
• MAC unit for reconfigurable systems using multi-operand adders with double carry-save encodingUgur Cini, Olcay Kurt. 1-4 [doi]
• Dynamically reconfigurable FFT processor for flexible OFDM baseband processingMário Lopes Ferreira, Amin Barahimi, João Canas Ferreira. 1-6 [doi]
• Tip-enhanced Raman scattering of 4H-SİC filmsRu Han, Danghui Wang. 1-4 [doi]
• Automatic design of approximate circuits by means of multi-objective evolutionary algorithmsRadek Hrbacek, Vojtech Mrazek, Zdenek Vasícek. 1-6 [doi]
• Implementation of a secured digital ultralight 14443-type A RFID tag with an FPGA platformYassine Naija, Vincent Beroulle, David Hély, Mohsen Machhout. 1-3 [doi]
• FPGA implementations of HEVC sub-pixel interpolation using high-level synthesisFiras Abdul Ghani, Ercan Kalali, Ilker Hamzaoglu. 1-4 [doi]
• Thikness dependence investigation of the mutual inductance link in concentric planar transformersHala Ghadhab, Mohamed Hadj Said, Fares Tounsi, Brahim Mezghani, Sandeep Goud Surya, V. Ramgopal Rao. 1-5 [doi]
• Register file reliability enhancement through adjacent narrow-width exploitationHamzeh Ahangari, Ihsen Alouani, Özcan Özturk, Smaïl Niar, Atika Rivenq. 1-4 [doi]
• Low power digital video compression hardware designIlker Hamzaoglu. 1 [doi]
• Efficient selection of critical paths for delay defects in the presence of process variationsPhaninder Alladi, Spyros Tragoudas. 1-6 [doi]
• High speed content addressable memory with reduced size and less power consumptionHammad Riaz, Abdul Aziz Bhatti, Muhammad Ashraf Tahir, Muhammad Sarwar. 1-6 [doi]
• Approximate computing for unreliable siliconAndreas Peter Burg. 1 [doi]
• Qualitative techniques for System-on-Chip test with low-energy protonsStefano Di Mascio, Marco Ottavi, Gianluca Furano, Tomasz Szewczyk, Alessandra Menicucci, Luigi Campajola, Francesco Di Capua. 1-6 [doi]
• Investigation of transfer-free catalytic CVD graphene on SiO2 by means of conductive atomic force microscopyD. Noll, Udo Schwalke. 1-4 [doi]
• FPGA implementation of a fault-tolerant application-specific NoC designSerif Yesil, Suleyman Tosun, Özcan Özturk. 1-6 [doi]
• Do you trust your chip?Ozgur Sinanoglu. 1 [doi]
• Voltage over-scaling in sequential circuits for approximate computingDavid May, Walter Stechele. 1-6 [doi]
• SEcube™: An open-source security platform in a single SoCAntonio Varriale, Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto, Pascal Trotta, Tiziana Margaria. 1-6 [doi]
• Optimizing CMOS analog Variable Gain Amplifier cell for WiMAX receiverSawssen Lahiani, Samir Ben Salem, Houda Daoud, Mourad Loulou. 1-6 [doi]
• Evolvable Hardware in FPGAs: Embedded tutorialRuben Salvador. 1-6 [doi]
• High-speed dynamic dual-rail ultra low voltage static CMOS logic operating at 300 mVOmid Mirmotahari, Ali Dadashi, Mehdi Azadmehr, Yngvar Berg. 1-4 [doi]
• Identification of delay defects on embedded paths using one current sensorWisam Aljubouri, Spyros Tragoudas, Themistoklis Haniotakis. 1-4 [doi]
• Multilevel operation in oxide based resistive RAM with SET voltage modulationHassen Aziza, Haithem Ayari, Santhosh Onkaraiah, Mathieu Moreau, Jean Michel Portal, Marc Bocquet. 1-5 [doi]
• An efficient mapping algorithm on 2-D mesh Network-on-Chip with reconfigurable switchesSalih Bayar, Arda Yurdakul. 1-4 [doi]
• Boolean logic gate exploration for memristor crossbarLei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels. 1-6 [doi]
• Lets move polymorphism downwards: On the multifunctional logic based on ambipolar behaviour of semiconductor devicesRichard Ruzicka, Radek Tesar. 1-5 [doi]
• Residue Number System as a side channel and fault injection attack countermeasure in elliptic curve cryptographyApostolos P. Fournaris, Louiza Papachristodoulou, Lejla Batina, Nicolas Sklavos. 1-4 [doi]
• A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testingYong Zhao, Hans G. Kerkhoff. 1-4 [doi]
• A high performance hardware for early terminated C-1BT based motion estimationAbdulkadir Akin, Ilker Hamzaoglu. 1-4 [doi]
• A novel heterogeneous FPGA architecture based on memristor-transistor hybrid approachUmer Farooq, M. Khurram Bhatti, M. Hassan Aslam. 1-6 [doi]
• Auto-adaptive ultra-low power ICAlberto Bosio, Philippe Debaud, Patrick Girard, Stephane Guilhot, Miroslav Valka, Arnaud Virazel. 1-6 [doi]