Table of Contents

• Memory Encryption Support for an FPGA-based RISC-V ImplementationAlessandro Cilardo. 1-5 [doi]
• Characterization of a RISC-V System-on-Chip under Neutron RadiationDouglas A. dos Santos, Lucas M. Luza, Maria Kastriotou, Carlo Cazzaniga, Cesar A. Zeferino, Douglas R. Melo, Luigi Dilillo. 1-6 [doi]
• Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip RouterDouglas Rossi Melo, Cesar Albenes Zeferino, Eduardo Augusto Bezerra, Luigi Dilillo. 1-6 [doi]
• Technology Impact on Neutron-Induced Effects in SDRAMs: A Comparative StudyLucas Matana Luza, Daniel Söderström, André Martins Pio de Mattos, Eduardo Augusto Bezerra, Carlo Cazzaniga, Maria Kastriotou, Christian Poivey, Luigi Dilillo. 1-6 [doi]
• Testing a RISCV-Like Architecture With an HDL-Based Virtual TesterNooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi. 1-6 [doi]
• Improving the Detection of Undefined State Faults in FinFET SRAMsG. Cardoso Medeiros, Moritz Fieback, Thiago Santos Copetti, Anteneh Gebregiorgis, Mottaqiallah Taouil, Leticia B. Poehls, Said Hamdioui. 1-6 [doi]
• Octantis: An Exploration Tool for Beyond von Neumann architecturesAndrea Marchesin, Giovanna Turvani, Andrea Coluccio, Fabrizio Riente, Marco Vacca, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni. 1-5 [doi]
• A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V ArchitectureLuca Zulberti, Pietro Nannipieri, Luca Fanucci. 1-6 [doi]
• Simulation of state of the art EEPROM programming window closure during endurance degradationFranck Matteo, Roberto Simola, Franck Melul, Karine Coulié, Jérémy Postel-Pellerin, Arnaud Régnier. 1-5 [doi]
• FeFET based Logic-in-Memory: an overviewCédric Marchand 0002, Ian O'Connor, Mayeul Cantan, Evelyn T. Breyer, Stefan Slesazeck, Thomas Mikolajick. 1-6 [doi]
• Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technologyPaul Devoge, Hassen Aziza, Philippe Lorenzini, Franck Julien, Abderrezak Marzaki, Alexandre Malherbe, Marc Mantelli, Thomas Sardin, Sébastien Haendler, Arnaud Régnier, Stephan Niel. 1-5 [doi]
• Design and Optimization of Cantilever Based RF-MEMS Shunt Switch for 5G ApplicationsHeba Saleh, Rayan Bajwa, Ibrahim Tekin, Murat Kaya Yapici. 1-4 [doi]
• Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test ValidationPraise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi 0001, Degang Chen. 1-6 [doi]
• On the Limitations of Concatenating Boolean Operations in Memristive-Based Logic-In-Memory SolutionsPietro Inglese, Elena Ioana Vatajelu, Giorgio Di Natale. 1-5 [doi]
• Toward an Implementation Modeling Methodology for Designing SCA resilient Cryptographic CircuitsGabriel Rocherolle, Roselyne Chotin. 1-4 [doi]
• Power Side Channel Attacks: Where Are We Standing?Mottaqiallah Taouil, Abdullah Aljuffri, Said Hamdioui. 1-6 [doi]
• A 270 Hz, Fine Frequency Tuning Class-C Oscillator Using Capacitive-Inductive Degeneration Technique in 130 -nm CMOSSehmi Saad, Fayrouz Haddad, Aymen Ben Hammadi. 1-6 [doi]
• Innovative methods for Burn-In related Stress Metrics ComputationWalter Ruggeri, Paolo Bernardi, Stefano Littardi, Matteo Sonza Reorda, Davide Appello, Claudia Bertani, Giorgio Pollaccia, Vincenzo Tancorre, Roberto Ugioli. 1-6 [doi]
• Impact of Data Pre-Processing Techniques on Deep Learning Based Power AttacksAbdullah Aljuffri, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil. 1-6 [doi]
• Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean SatisfiabilityPayam Habiby, Sebastian Huhn 0001, Rolf Drechsler. 1-4 [doi]
• Design Space Exploration Applied to SecurityAntoine Linarès, David Hély, Frank Lhermet, Giorgio Di Natale. 1-4 [doi]
• Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technologyRomeric Gay, Vincenzo Della Marca, Hassen Aziza, Arnaud Régnier, Stephan Niel, Abderrezak Marzaki. 1-4 [doi]
• RGB and 3D-Segmentation Data Combination for the Autonomous Object Manipulation in Personal Care RoboticsGiovanni Mezzina, Daniela De Venuto. 1-6 [doi]
• Microarchitecture-aware Fault Models: Experimental Evidence and Cross-Layer Inference MethodologyIhab Alshaer, Brice Colombier, Christophe Deleuze, Vincent Beroulle, Paolo Maistri. 1-6 [doi]
• Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing ArchitecturesL. Ammoura, Marie-Lise Flottes, P. Girard, Arnaud Virazel. 1-4 [doi]