Abstract is missing.
- Challenges in Consumer Electronics for the 21st CenturySteve Leibson. 3-12
- Scientific Computing using Reconfigurable HardwareViktor K. Prasanna. 13
- A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative EvaluationJürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet. 14-24
- An Integrated Platform for Heterogeneous Reconfigurable ComputingBernard Pottier. 25-36
- Energy-Efficient Dynamic Task Scheduling Algorithm for Reconfigurable System-on-Chip ArchitecturesSwathi Tanjore Gurumani, B. Earl Wells. 37-43
- Memory Hierarchy for MCSoPC Multithreaded SystemsErik Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David L. Andrews. 44-50
- Design Space Exploration of Multiprocessor Systems with MultiContext Reconfigurable Co-ProcessorsPranav Vaidya, Jaehwan John Lee. 51-60
- Energy-Aware System Synthesis for Reconfigurable Chip MultiprocessorsXiaofang Wang, Sotirios G. Ziavras, Jie Hu. 61-70
- HW implementation of an execution manager for reconfigurable systemsJavier Resano, Juan Antonio Clemente, Carlos Gonzalez, Jose Luis Garcia, Daniel Mozos. 71-77
- Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-SimilarityMatteo Giani, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto. 78-84
- Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable ArchitecturesFredy Rivera, Marcos Sanchez-Elez, Nader Bagherzadeh. 85-91
- A Compiler to Generate Hardware from Java Byte Codes for High Performance, Low Energy Embedded SystemsDarrin M. Hanna, Michael DuChene, Lawrence Kennedy, Brian Carpenter. 92-98
- Selecting Heterogeneous Computation Blocks for Reconfigurable JPEG Codec ComputingWei-Ting Wang, Wai-Hong Tam, Yi-Chi Chen, Kuen-Cheng Chiang, Chung-Ping Chung. 99-106
- High-Precision BLAS on FPGA-enhanced ComputersChuan He, Guan Qin, Richard E. Ewing, Wei Zhao. 107-116
- High-efficiency protection solution for off-chip memory in embedded systemsRomain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Wayne Burleson. 117-123
- Simulation Framework for Performance Prediction in the Engineering of Reconfigurable Systems and ApplicationsEric Grobelny, Casey Reardon, Adam Jacobs, Alan D. George. 124-130
- FPGA Implementation of an Analytical Design Method for A Cycle-Optimal 2D-DCT/IDCTMichaela Amoo, Clay Gloster. 131-137
- Prototyping of a Two-Phase Micropipeline on FPGAsAbdel Ejnioui. 138-146
- A New Routing Approach to Minimizing FPGA Reconfiguration DataWeinan Chen, Chenglian Peng, Bo Zhou. 147-151
- Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial ArchitectureFlorian Dittmann, Achim Rettberg, Raphael Weber. 152-158
- An FPGA Implementation of Reciprocal Sums for SPMESam Lee, Paul Chow. 159-165
- Optimization of Shared High-Performance Reconfigurable Computing ResourcesMelissa Smith, Gregory Peterson. 166-174
- Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable HardwareChristophe Wolinski, Krzysztof Kuchcinski. 175-181
- Critical Path Delay Reduction in FPGAs with Unbalanced Lookup TimesJason Meyer, Fatih Kocan, Daniel G. Saab. 182-190
- Reducing the reconfiguration overhead: a survey of techniquesElena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor. 191-194
- Implementing the G.723.1 Speech Codec Using a Coarse-Grained Reconfigurable CoprocessorHenrik Svensson, Thomas Lenart, Viktor Öwall. 195-198
- Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAsCristiana Bolchini, Fabio Salice, Marco D. Santambrogio. 199-202
- Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable ProcessorVu Manh Tuan, Yohei Hasegawa, Hideharu Amano. 203-206
- Agent-Based Reconfigurability for Fault-Tolerance in Network-on-ChipPekka Rantala, Jouni Isoaho, Hannu Tenhunen. 207-210
- Design and Evaluation of a Software Infrastructure for the Runtime Management of Reconfigurable ResourcesDimitris Syrivelis, Spyros Lalis. 211-215
- Evolvable Hardware: A Functional Level Evolution Framework Based on ImpulseCAnna Antola, Marco Castagna, Pamela Gotti, Marco D. Santambrogio. 216-219
- Autonomous Computing Systems: A Proposed RoadmapNeil Steiner, Peter Athanas. 220-226
- A TCP/IP Fragmentation Monitoring Core For Intrusion PreventionVukasin Pejovic, Slobodan Bojanic, Carlos Carreras. 227-230
- Pure ASIC-Based Retargetable Computing: Architectures, Advantages, and ChallengesYong-Kyu Jung. 231-237
- Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAsJens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann. 238-247
- A Sandbox for Exploring the OpenFire ProcessorAlex Marschner, Stephen D. Craven, Peter M. Athanas. 248-251
- Power Efficient Domain-Specific Reconfigurable Architectures for System-on-Chip ApplicationsArjun K. Pai, Khaled Benkrid. 252-258
- 272 Gate Count Optically Differential Reconfigurable Gate Array VLSIMinoru Watanabe, Takenori Shiki, Fuminori Kobayashi. 259-264
- FPGA Implementation of a Reconfigurable License Plate Detection MethodLudek Bryan, Otto Fucík. 265-268
- Performance Evaluation of Two Allocation Schemes for Combinatorial Group Testing Fault IsolationRawad N. Al-Haddad, Carthik A. Sharma, Ronald F. DeMara. 269-272
- Efficient FPGA-based Implementation of Time Synchronization for MIMO-OFDMJeoong Sung Park, Hong-Jip Jung. 273-279
- High-Level Specification of Runtime Reconfigurable DesignsStephen D. Craven, Peter M. Athanas. 280-283
- A Scalable and Reconfigurable Shared-Memory Graphics Cluster ArchitectureRoss Brennan, Michael Manzke, Keith O Conor, John Dingliana, Carol O Sullivan. 284-290
- Optimization of Reconfiguration-speed Control Bits for an Optically Reconfigurable Gate ArrayMinoru Watanabe. 291-294
- Feasibility of Hardware Acceleration of a Neocortex ModelSébastien Lafontant, Tarek Taha. 295-301
- Autonomous Computing Systems: A Proof-of-ConceptNeil Steiner, Peter M. Athanas. 302