Table of Contents

• Multicore Devices: A New Generation of Reconfigurable ArchitecturesSteven A. Guccione. 3-11
• Reconfigurable Mesh Techniques and ApplicationsJerry L. Trahan. 15-28
• On FPGA Design with Self-checking and Fault Tolerance CapabilityParag K. Lala. 29-34
• The GOmputer: Accelerating GO with FPGAsMarco Platzner, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz, Tobias Schumacher, Andre Send, Alexander Warkentin. 35-45
• Modeling Abstractions for Next Generation Reconfigurable ComputingDavid L. Andrews, Jason Agron. 49-56
• Design Productivity for Configurable ComputingBrent E. Nelson, Michael J. Wirthlin, Brad L. Hutchings, Peter M. Athanas, Shawn Bohner. 57-66
• FPGAs or Distributed Systems?Bernard Pottier. 67-75
• A New Tact in Reconfigurable Computing ResearchJohn Watson, Steven H. Kelem, Brian Box, Joseph Hassoun, Stephen Wasson, Bob Plunkett, Chris Phillips. 76-78
• Industrial Workshop - Architectural Synthesis for Reconfigurable ComputingChris Eddington. 79
• Communication and Synchronization in Multithreaded Reconfigurable Computing SystemsEnno Lübbers, Marco Platzner. 83-89
• A New High Performance Multi Gigabit String Matching EngineGeorges Adouko, François Charot, Christophe Wolinski. 90-96
• Towards Understanding and Managing the Dynamic Behavior of Run-Time Reconfigurable ArchitecturesKehuai Wu, Esben Rosenlund Hansen, Jan Madsen. 97-103
• System on a Programmable Chip Adaptation Through Active Partial ReconfigurationErik Anderson, Matthew French, Dong-In Kang. 104-110
• A New Efficient Architecture for Univariate Polynomial Interpolation Over GF(2:::m:::)Edgar Ferrer, Dorothy Bollman. 111-115
• A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and RoutabilityWai-Chung Tang, Catherine L. Zhou, Yu-Liang Wu. 116-121
• Design Framework for Partial Run-Time FPGA ReconfigurationChris Conger, Ann Gordon-Ross, Alan D. George. 122-128
• Elemental Computing for High ReliabilityJoseph Hassoun, Steve Kelemjoseph, Brian Box, Stephen Wasson, Bob Plunkett, Chris Phillips. 129-135
• An Introduction to Radiation-Induced Failure Modes and Related Mitigation Methods For Xilinx SRAM FPGAsHeather Quinn, Paul Graham, Keith Morgan, Jim Krone, Michael Caffrey, Michael J. Wirthlin. 139-145
• Multiparadigm Computing for Space-Based Synthetic Aperture RadarAdam Jacobs, Grzegorz Cieslewski, Casey Reardon, Alan D. George. 146-152
• TMR with More Frequent Voting for Improved FPGA ReliabilityBrian Pratt, Michael Caffrey, Derrick Gibelyou, Paul Graham, Keith Morgan, Michael J. Wirthlin. 153-158
• Highly Parallel FPGA Based IEEE-754 Compliant Double-Precision Floating-Point DivisionSandeep K. Venishetti, Ali Akoglu. 159-165
• SystemC-based Custom Reconfigurable Cores for Wireless ApplicationsAli Ahmadinia, Balal Ahmad, Ahmet T. Erdogan, Tughrul Arslan. 169-175
• A Formal Semantics for Control and Data flow in the Gannet Service-based System-on-Chip ArchitectureWim Vanderbauwhede. 176-183
• Optimizing Pipelining in HDL Generated Automatically from C Source CodesWesley Holland, Yoginder S. Dandass. 184-190
• A Framework to Improve IP Portability on Reconfigurable ComputersMiaoqing Huang, Ivan Gonzalez, Sergio López-Buedo, Tarek A. El-Ghazawi. 191-197
• Implementation of a Multi-Context FPGA Based on Flexible-Context-PartitioningHasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama. 201-207
• A Method for Capturing State Data on Dynamically Reconfigurable ProcessorsVu Manh Tuan, Hideharu Amano. 208-214
• Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEsMasaru Kato, Yohei Hasegawa, Hideharu Amano. 215-221
• MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 PerspectiveFuminori Kobayashi, Yasuyuki Morikawa, Minoru Watanabe. 222-228
• Fast Real-Time LIDAR Processing on FPGAsKuei-Tsung Shih, Arjun Balachandran, Karthik Nagarajan, Brian Holland, K. Clint Slatton, Alan D. George. 231-237
• Gradient Run-length Data Compression for Real-time Airborne Image ProcessingZachary K. Baker, Justin L. Tripp. 238-244
• A Hardware Accelerator for k-th Nearest Neighbor ThinningTobias Schumacher, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian Plessl, Marco Platzner. 245-251
• A Parallel Array to Accelerate GFA Modeling in Video CodingAbdel Ejnioui, Paul Bao. 252-258
• Qnet: A Modular Architecture for Reconfigurable ComputingScott Lloyd, Quinn Snell. 259-265
• Scalable FPGA Architecture for DCT Computation Using Dynamic Partial ReconfigurationJian Huang, Matthew Parris, Jooheung Lee, Ronald F. DeMara. 269-272
• SCARS: Scalable Self-Configurable Architecture for Reusable Space SystemsAdarsha Sreeramareddy, Jeff Josiah, Ali Akoglu. 273-276
• Selection and Use of Programmable Logic in Flight ApplicationsGary Block, Paula Pingree, Yungling Lou. 277-280
• Hardware/Software Co-designed Extended Kalman Filter on an FPGARobert Barnes, Aravind Dasu. 281-284
• Multi-Criteria Optimization and Performance Measurement of Domain-Specific Reconfigurable Architectures Targeting Image and Video Processing ApplicationsArjun K. Pai, Khaled Benkrid. 285-288
• A 770ns Holographic Reconfiguration of a Four-Context DORGAMao Nakajima, Minoru Watanabe. 289-292
• Dynamically Reconfigurable FFTs for Cognitive Radio on a Multiprocessor PlatformQiwei Zhang, Karel Walters, André B. J. Kokkeler, Gerard J. M. Smit. 293-297
• High Performance Double Precision Reduction Circuit Implementation in FPGAAndrea Suardi, Antonio Manenti, Andrea Abba, Angelo Geraci. 298-301
• A Cellular Automata ASIC for Conformal ComputingMariam Hoseini, Chao You, Mark Pavicic. 305-306
• Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw systemAngel Luis González Bravo, Hortensia Mecha, Julio Septién, Sara Román Navarro, Daniel Mozos. 307-308
• Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching SignalsMasanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama. 309-310
• FPGA Schemes with Optimized Routing for the Advanced Encryption StandardJason Van Dyken, José G. Delgado-Frias, Sirisha Medidi. 311-312
• Performance Evaluation of FPGA-based Hardware Accelerator: A Case StudyYidong Liu, Srinivasan Santhanam, Jooheung Lee. 313-314
• FPGA Resource Management Using Internal RAM as Aata CacheLaura Sanchez, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo. 317-318
• Resource Management for Hw Multitasking in Three Dimensional FPGAsJose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo. 319-320
• The Viability of Cellular Automata Architectures for General Purpose ComputingVictor V. Zhirnov, Greg Leeming, Kosmas Galatsis, Ralph K. Cavin III. 321-333
• Threats and Challenges in Reconfigurable Hardware SecurityRyan Kastner, Ted Huffmire. 334-345
• High Level Languages for Reconfigurable Computing: An Equivalent to Third Generation Software Languages?Gavin Smith, Grant B. Wigley. 346-352