Table of Contents

• Design-for-Test and Calibration for Silicon Photonics using Ring Resonators and Wavelength Division MultiplexingPratishtha Agnihotri, Lawrence M. Schlitt, Priyank Kalla, Steve Blair. 1-6 [doi]
• On the Fault Sensitivity of Natural Language Embeddings ComputationSumeet Sapkal, Ussama Zahid, Giulio Gambardella, Haralampos-G. Stratigopoulos, Brian Clerkin. 1-6 [doi]
• A UCIe Compatible Repair Scheme for the Clustered Faults in the Hexagonal Array of Interconnect LanesZhaohong Lin, Xiaole Cui, Juncheng Pu, Huan Yang. 1-4 [doi]
• Early Result Capture: Racing Conditions in Pipeline due to Clock GlitchesRoua Boulifa, Paolo Maistri, Giorgio Di Natale. 1-6 [doi]
• On the Trustworthiness of Spiking Neural Networks and Neuromorphic SystemsTheofilos Spyrou, Haralampos-G. Stratigopoulos, Ihsen Alouani, Said Hamdioui, Anteneh Gebregiorgis. 1-10 [doi]
• DFT Techniques For Efficient 3D IC Interconnect Test For Chiplet and Multi-Die PackageAnshuman Chandra, Chi-Chun Yang, Quoc Phan, Martin Keim. 1-6 [doi]
• AI-Assisted Framework for Real-Time Monitoring and Management of Probe Cards in Electrical Wafer Sort ApplicationsMehdi Bejani, Davide Appello, Marco Mauri, Simone Todaro, Stefano Mariani. 1-4 [doi]
• 2I-TEST for Chiplet-based Inter-die InterconnectsPo-Yao Chuang, Erik Jan Marinissen. 1-6 [doi]
• Security Risks in AI Accelerators: Detecting RTL Vulnerabilities to Model Theft with Formal VerificationMohamed Shelkamy Ali, Lucas Deutschmann, Johannes Müller 0006, Anna Lena Duque Antón, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz. 1-6 [doi]
• Modeling and Analysis of Aging Impact on SRAM PUFs for Advanced FinFET Technology NodesShayesteh Masoumian, Roel Maes, Noemie Beringuier-Boher, Karthik Keni Yerriswamy, Geert Jan Schrijen, Said Hamdioui, Mottaqiallah Taouil. 1-4 [doi]
• Automated Test Equipment Drift Characterization Based on Gauge Repeatability and ReproducibilityAnand Venkatachalam, Ernst Aderholz, Matthias Sauer 0002, Simon Schweizer, Matthias Werner, Ilia Polian. 1-6 [doi]
• Reliability Under Stress: The Impact of Localized Aging on RO-PUF Architectures in FPGAsAghiles Douadi, Elena Ioana Vatajelu, Paolo Maistri, David Hély, Vincent Beroulle, Giorgio Di Natale. 1-4 [doi]
• Silent Data Corruption: DRAM Root Causes and Ways of Improving Test Quality Towards 0ppmChenyu Fang, Peter Poechmueller. 1-4 [doi]
• Holistic Memory DFT Partitioning Using a Convolution-Based AlgorithmOlivier Romain, Wojciech Gierszal, Luc Romain, Artur Pogiel. 1-4 [doi]
• Pulsed Electromagnetic Fault Injection Attack on Ring Oscillator-based PUFs in FPGAsSami El Amraoui, Aghiles Douadi, Régis Leveugle, Paolo Maistri. 1-4 [doi]
• Automatic Test Pattern Generation for Printed Neuromorphic CircuitsTara Gheshlaghi, Priyanjana Pal, Alexander Studt, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori. 1-6 [doi]
• In-Field Monitoring and Preventing Read Disturb Faults in RRAMsHanzhi Xun, Moritz Fieback, Sicong Yuan, Changhao Wang, Erbing Hua, Hassen Aziza, Leticia Bolzani Poehls, Riccardo Cantoro, Rajendra Bishnoi, Mottaqiallah Taouil, Said Hamdioui. 1-6 [doi]
• Securing Reconfigurable Scan Networks Against Data Sniffing and Data Alteration AttacksJoel Åhlund, Markus Törmänen, Mikael Kerttu, Pamela Svensson, Torbjörn Månefjord, Christian Johansson, Erik Larsson. 1-6 [doi]
• Pin Electronics for Instrumentation and Automated Test Equipment: Challenges and SolutionsSandeep D'Souza, Matthew Getz, Patrick Sullivan, Joseph Peraza, Gerwin Veltink, Paul Van Ulsen. 1-4 [doi]
• Self-Aware Silicon: Enhancing Lifecycle Management with Intelligent Testing and Data InsightsFabian Vargas 0001, Marko S. Andjelkovic, Milos Krstic, Anirban Kar, Swati Deshwal, Yogesh S. Chauhan, Hussam Amrouch, Daniel Tille, Sebastian Huhn 0001. 1-10 [doi]
• Multi-Context Execution on a RISC-V Core for Mixed-Criticality SystemsLeonardo Fazzini, Giacomo Valente, Fabio Federici, Matthew P. Corbett, Tania Di Mascio. 1-4 [doi]
• Confidence Driven Compact Testing of Compute-in-Memory Based Language ModelsAnurup Saha, Chandramouli N. Amarnath, Kwondo Ma, Abhijit Chatterjee. 1-6 [doi]
• Machine Learning-Assisted Side-Channel Analysis for Software Integrity VerificationNiklas Lindskog, Håkan Englund, Jakob Sternby, Elena Dubrova. 1-6 [doi]
• Optimizing RO-PUFs: A Filtering Approach to Reliability and Entropy Trade-offsVasilii Kulagin, Giorgio Di Natale, Elena Ioana Vatajelu. 1-4 [doi]
• Heterogeneous Integration of Advanced CMOS and Emerging Devices: Challenges and SolutionsLetícia M. Bolzani Pöhls, André Lucas Chinazzo, Mahdi Benkhelifa, Anirban Kar, Hussam Amrouch, Milos Krstic. 1-9 [doi]
• FastGDBN: A GPU-Accelerated DNN for Identifying Good Dies in Bad NeighborhoodsYu-Heng Tsao, Yu-Guang Chen. 1-6 [doi]
• Structural Testing of a RRAM-based AI Accelerator CoreEmmanouil Anastasios Serlis, Hanzhi Xun, Mottaqiallah Taouil, Said Hamdioui, Moritz Fieback. 1-6 [doi]
• FLARE: Fault Attack Leveraging Address Reconfiguration Exploits in Multi-Tenant FPGAsJayeeta Chaudhuri, Hassan Nassar, Dennis R. E. Gnad, Jörg Henkel, Mehdi B. Tahoori, Krishnendu Chakrabarty. 1-6 [doi]
• Identification of Failing Flip-Flops with Triangular Test Response CompactionGrzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer. 1-6 [doi]
• SiFFS: A Scalable in-Fault Functional Simulation Framework for Fault Criticality AnalysisHaripriya R. S, Naveen Kollepara, Jaynarayan T. Tudu. 1-4 [doi]
• Robust Pattern Generation for Small Delay Faults under the Impact of VariationsHanieh Jafarzadeh, Sybille Hellebrand, Hans-Joachim Wunderlich. 1-2 [doi]
• Optimized MBIST-Based MRAM Testing for Automotive MCUs to Achieve Superior Performance and Quality AssuranceVinayak Bharat Naik, Gregory Billus, Amit Kumar Shukla, Andre Vogel, Veit Kriegerstein, Patrick Scharf, Venkata Siva Komma, Johannes Mueller, Thomas Merbeth, Ralf Flemming, Ingolf Lorenz, Muthu Kumaran Nambi, Ee Ee Yeoh, Hemavathi Chaya, Siddharth Gupta, Yentsai Huang, Sushma Sambatur, Joerg Winkler, Tom Andre, Shane Hollmer, Steven Soss, Jongsin Yun, Wei Zou, Harshitha Kodali, Luc Romain, Albert Au, Lori Schramm, Martin Keim. 1-4 [doi]
• Non-Uniform Error Correction for Hyperdimensional Computing Edge AcceleratorsMahboobe Sadeghipour Roodsari, Surendra Hemaram, Mehdi B. Tahoori. 1-6 [doi]
• LLM-aided Test Generation for Custom Neural Network Hardware AcceleratorsFederico Nicolás Peccia, Tobias Hald, Oliver Bringmann 0001. 1-6 [doi]
• An Integrated Framework for Aging Analysis Based on an Age-Aware Cell LibraryAmirmahdi Joudi, Negin Safari, Fatemeh Mohammadzadeh, Katayoon Basharkhah, Fatemeh Sheikhshoaei, Zainalabedin Navabi. 1-6 [doi]
• MBIST-guided Reliability Improvement Scheme for SRAM-based Computation in MemorySina Bakhtavari Mamaghani, Jongsin Yun, Martin Keim, Mehdi Baradaran Tahoori. 1-6 [doi]
• Testing Functional Interfaces And Complex PADs Within Multi-Die Packages With IEEE P3405Anshuman Chandra, Nir Sever, Martin Keim. 1-4 [doi]
• Dependable Neuromorphic Computing-in-Memory ArchitecturesFarhad Merchant, Ankit Bende, Markus Fritscher, Shahar Kvatinsky, Simranjeet Singh, Vikas Rana, Regina Dittmann, Keerthi Dorai Swamy Reddy, Christian Wenger, Fouwad Jamil Mir, Mottaqiallah Taouil, Manil Dev Gomony, Said Hamdioui, Henk Corporaal. 1-10 [doi]
• BISSEL: Built-In Self Security via Embedded Sensors for Reproducible Side-Channel Leakage AssessmentMd Toufiq Hasan Anik, Hasin Ishraq Reefat, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi. 1-6 [doi]
• Synergistic Built-In ECC Repair (BIER) Technique for Enhancing Yield and Reliability of Flash MemoryShyue-Kung Lu, Chun-Kai Chao, Kohei Miyase. 1-4 [doi]
• Computing with Printed and Flexible ElectronicsMehdi B. Tahoori, Emre Ozer, Georgios Zervakis 0001, Konstantinos Balaskas, Priyanjana Pal. 1-9 [doi]
• European Test Symposium Teams: an Anniversary SnapshotMaksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rold Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, G. Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, A. Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand. 1-48 [doi]
• Physical Unclonable Functions (PUFs): Foundations, Evaluation, and Testing for Secure Hardware SystemsSergio Vinagrero Gutierrez, Giorgio Di Natale, Elena Ioana Vatajelu. 1-10 [doi]
• FSMlock: Defending against Oracle-based Sequential Logic-Locking Attacks under Output-Corruption RequirementsIoannis Stavrinos, Christos Chalagiannis, Emmanouil Kalligeros. 1-4 [doi]
• Local Trimming Method for Enhancing the Read Reliability of STT-MRAMsPei Yun Lin, Jin-Fu Li 0001. 1-4 [doi]
• MTMS: Age-Aware Multi-Task Multi-Layer Stacking for SSD Failure PredictionGuo Li, Zijun Jing, Jing Li, Jianli Ding. 1-4 [doi]
• Large Language Models (LLMs) for Verification, Testing, and DesignChandan Kumar Jha 0001, Muhammad Hassan 0001, Khushboo Qayyum, Sallar Ahmadi-Pour, Kangwei Xu, Ruidi Qiu, Jason Blocklove, Luca Collini, Andre Nakkab, Ulf Schlichtmann, Grace Li Zhang, Ramesh Karri, Bing Li, Siddharth Garg, Rolf Drechsler. 1-10 [doi]
• Multi Coefficient CPA on a Black Box Hardware Implementation of CRYSTALS-KyberTarick Welling, Maël Gay, Ilia Polian. 1-6 [doi]
• Analysis and Mitigation of Radiation Effects in SRAM-based Register FilesZhe Zhang, Surendra Hemaram, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian. 1-4 [doi]
• A Novel BIST Method for Multi-Port Register FilesAndy Chen, Vianney Choserot, Munish Kumar, Khushal Gelda, Shreyas Pramod Dixit, Wei Zou, Jongsin Yun, Harshitha Kodali, Albert Au, Lori Schramm, Martin Keim. 1-6 [doi]
• Towards Understanding of System-Level Test Unique FailsNourhan Elhamawy, Jens Anders, Ilia Polian, Matthias Sauer 0002. 1-4 [doi]
• Synthesizing 56 Gbps NRZ Test Signals Using FPGAs and SiGe LogieDavid Keezer, Cao Wang, Shengbo Liu. 1-4 [doi]