Abstract is missing.
- An FPGA architecture for DRAM-based systolic computationsNorman Margolus. 2-11 [doi]
- Garp: a MIPS processor with a reconfigurable coprocessorJohn R. Hauser, John Wawrzynek. 12-21 [doi]
- A time-multiplexed FPGASteven Trimberger, Dean Carberry, Anders Johnson, Jennifer Wong. 22-29 [doi]
- An FPGA-based coprocessor for ATM firewallsJohn T. McHenry, Patrick W. Dowd, Frank A. Pellegrino, Todd M. Carrozzi, W. B. Cocks. 30-39 [doi]
- A wireless LAN demodulator in a Pamette: design and experienceTom McDermott, Philip J. Ryan, Mark Shand, David J. Skellern, Terry Percival, Neil Weste. 40-46 [doi]
- Incremental reconfiguration for pipelined applicationsHerman Schmit. 47-55 [doi]
- Compilation tools for run-time reconfigurable designsWayne Luk, Nabeel Shirazi, Peter Y. K. Cheung. 56-65 [doi]
- A dynamic reconfiguration run-time systemJim Burns, Adam Donlin, Jonathan Hogg, Satnam Singh, Mark De Wit. 66-76 [doi]
- The swappable logic unit: a paradigm for virtual hardwareGordon J. Brebner. 77-86 [doi]
- The Chimaera reconfigurable functional unitScott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao. 87-97 [doi]
- Computing kernels implemented with a wormhole RTR CCMRay A. Bittner, Peter M. Athanas. 98-105 [doi]
- Mapping applications to the RaPiD configurable architectureCarl Ebeling, Darren C. Cronquist, Paul Franklin, Jason Secosky, Stefan G. Berg. 106-115 [doi]
- Defect tolerance on the Teramac custom computerW. Bruce Culbertson, Rick Amerson, Richard J. Carter, Philip Kuekes, Greg Snider. 116-124 [doi]
- Systems performance measurement on PCI PametteLaurent Moll, Mark Shand. 125-133 [doi]
- The RAW benchmark suite: computation structures for general purpose computingJonathan Babb, Matthew Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael Bedford Taylor, Jang Kim, Devabhaktuni Srikrishna, Anant Agarwal. 134-144 [doi]
- Automated field-programmable compute accelerator design using partial evaluationQiang Wang, David M. Lewis. 145-154 [doi]
- FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again)Roger Woods, Stefan H.-M. Ludwig, Jean-Paul Heron, David W. Trainor, Stephan W. Gehring. 155-164 [doi]
- High level compilation for fine grained FPGAsMaya Gokhale, D. Gomersall. 165-174 [doi]
- Acceleration of an FPGA routerPak K. Chan, Martine D. F. Schlag. 175-181 [doi]
- Fault simulation on reconfigurable hardwareMiron Abramovici, Premachandran R. Menon. 182-191 [doi]
- Automated target recognition on SPLASH 2Michael Rencher, Brad L. Hutchings. 192-200 [doi]
- Real-time stereo vision on the PARTS reconfigurable computerJohn Woodfill, Brian Von Herzen. 201-210 [doi]
- Increased FPGA capacity enables scalable, flexible CCMs: an example from image processingJack Greenbaum, Michael Baxter. 211-218 [doi]
- Comparison of arithmetic architectures for Reed-Solomon decoders in reconfigurable hardwareChristof Paar, Martin Rosner. 219-225 [doi]
- Implementation of single precision floating point square root on FPGAsYamin Li, Wanming Chu. 226-233 [doi]
- Datapath-oriented FPGA mapping and placement for configurable computingTimothy J. Callahan, John Wawrzynek. 234-235 [doi]
- Mapping a real-time video algorithm to a context-switched FPGASteven H. Kelem. 236-237 [doi]
- A parallel hardware evolvable computer POLYPUwe Tangen, Ludger Schulte, John S. McCaskill. 238-239 [doi]
- Laser defect correction applications to FPGA based custom computersGlenn H. Chapman, Benoit Dufort. 240-241 [doi]
- Speech recognition HMM training on reconfigurable parallel processorHyun-Kyu Yun, Aaron Smith, Harvey F. Silverman. 242-243 [doi]
- Efficient implementation of the DCT on custom computersNeil W. Bergmann, Yuk Ying Chung, Bernard K. Gunther. 244-245 [doi]
- On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessorJason Cong, John Peck. 246-248 [doi]