Abstract is missing.
- Design of a VLIW Compute Accelerator on the Transmogrifier-2L. Louis Zhang, Qiang Wang, David M. Lewis. 3-12 [doi]
- A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability ProblemsMark J. Boyd, Tracy Larrabee. 13-21 [doi]
- Configuration Caching Management Techniques for Reconfigurable ComputingZhiyuan Li, Katherine Compton, Scott Hauck. 22-38 [doi]
- A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing SystemsPrithviraj Banerjee, U. Nagaraj Shenoy, Alok N. Choudhary, Scott Hauck, C. Bachmann, Malay Haldar, Pramod G. Joisha, Alex K. Jones, Abhay Kanhere, Anshuman Nayak, S. Periyacheri, M. Walkden, David Zaretsky. 39-48 [doi]
- Stream-Oriented FPGA Computing in the Streams-C High Level LanguageMaya Gokhale, Janice M. Stone, Jeffrey M. Arnold, Mirek Kalinowski. 49-58 [doi]
- A Reconfigurable Computing Architecture for MicrosensorsStephen M. Scalera, Mark Falco, Brent E. Nelson. 59-67 [doi]
- FPGA Implementation of a Microcoded Elliptic Curve Cryptographic ProcessorK. H. Leung, K. W. Ma, W. K. Wong, Philip Heng Wai Leong. 68-76 [doi]
- Customizing Graphics Applications: Techniques and Programming InterfaceHenry Styles, Wayne Luk. 77-90 [doi]
- Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing EnginesPedro C. Diniz, Joonseok Park. 91-100 [doi]
- A C to HDL Compiler for Pipeline Processing on FPGAsTsutomu Maruyama, Tsutomu Hoshino. 101-112 [doi]
- High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm)Cameron Patterson. 113-121 [doi]
- A Bit-Serial Implementation of the International Data Encryption Algorithm IDEAM. P. Leong, Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong. 122-131 [doi]
- An Adaptive Cryptographic Engine for IPSec ArchitecturesAndreas Dandalis, Viktor K. Prasanna, José D. P. Rolim. 132-144 [doi]
- Death of the RLOC?Satnam Singh. 145-152 [doi]
- Automated Extraction of Run-Time Parameterizable Cores from Programmable Device ConfigurationsPhilip James-Roxby, Steven A. Guccione. 153-164 [doi]
- Dynamic Fault Tolerance in FPGAs via Partial ReconfigurationJohn M. Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici. 165-174 [doi]
- An ACS Robotic Control Algorithm with Fault Tolerant CapabilitiesShu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey. 175-184 [doi]
- Tunable Fault Tolerance for Runtime Reconfigurable ArchitecturesSteven K. Sinha, Peter Kamarchik, Seth Copen Goldstein. 185-194 [doi]
- Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAsChris Dick, Fred Harris, Michael Rice. 195-204 [doi]
- Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication SystemsAhmad Alsolaim, Janusz A. Starzyk, Jürgen Becker, Manfred Glesner. 205-216 [doi]
- Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable HardwareBenjamin A. Levine, R. Reed Taylor, Herman Schmit. 217-226 [doi]
- Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation EngineEuripides Sotiriades, Apostolos Dollas, Peter Athanas. 227-235 [doi]
- An FPGA-Based Coprocessor for the Parsing of Context-Free GrammarsCristian Ciressan, Eduardo Sanchez, Martin Rajman, Jean-Cédric Chappelier. 236-248 [doi]
- A Reliable LZ Data Compressor on Reconfigurable CoprocessorsWei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey. 249-258 [doi]
- EVIDENCE: An FPGA-Based System for Photon EVent IDENtification and CEntroidingMonica Alderighi, Sergio D Angelo, Giacomo R. Sechi. 259-266 [doi]
- Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable HardwareMichael J. Wirthlin, Steve Morrison, Paul Graham, Brian Bray. 267-278 [doi]
- Configuration Relocation and Defragmentation for Reconfigurable ComputingKatherine Compton, James Cooley, Stephen Knol, Scott Hauck. 279-280 [doi]
- Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHWTsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara. 281-282 [doi]
- Hardware Accelerator for Subgraph Isomorphism ProblemsShuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi. 283-284 [doi]
- A Reconfigurable Hardware Platform for Digital Real-Time Signal Processing in Television StudiosK. Henriss, Peter Rüffer, Rolf Ernst, S. Hasenzahl. 285-286 [doi]
- Reconfigurable Array Media Processor (RAMP)Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley. 287-288 [doi]
- Internet Connected FPGAsHamish Fallside, Michael John Sebastian Smith. 289-290 [doi]
- A Reconfigurable Stochastic Model Simulator for Analysis of Parallel SystemsOu Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano. 291-294 [doi]
- A Virtual Hardware System on a Dynamically Reconfigurable Logic DeviceYuichiro Shibata, Masaki Uno, Hideharu Amano, K. Furuta, Taro Fujii, Masato Motomura. 295-296 [doi]
- Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable ArchitecturesRafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh. 297-298 [doi]
- A Communication Scheduling Algorithm for Multi-FPGA SystemsJinwoo Suh, Dong-In Kang, Stephen P. Crago. 299-300 [doi]
- Preemptive Multitasking on FPGAsL. Levinson, Reinhard Männer, M. Sessler, Harald Simmler. 301-302 [doi]
- BigSky-An On-Line Arithmetic Design Tool for FPGAsAaron Schneider, Robert McIlhenny, Milos D. Ercegovac. 303-304 [doi]
- Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design MappingsPaul Graham, Brad L. Hutchings, Brent E. Nelson. 305-306 [doi]
- Multiple Precision for Resource MinimizationGeorge A. Constantinides, Peter Y. K. Cheung, Wayne Luk. 307-308 [doi]
- StReAm: Object-Oriented Programming of Stream Architectures Using PAM-BloxOskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn. 309-312 [doi]
- An FPGA-Based Array Processor for an Ionospheric-Imaging RadarTim Tuan, Miguel Figueroa, Frank Lind, Chucai Zhou, Chris Diorio, John Sahr. 313-314 [doi]
- Embedded Compilation for Multimedia ApplicationsNathaniel D. Daw, Seth Copen Goldstein, Dennis Strelow. 315-316 [doi]
- Interfacing Reconfigurable Logic with a CPUKip Walker, Mihai Budiu, Seth Copen Goldstein. 317-318 [doi]
- A Run-Time Reconfigurable Plug-In for the Winamp MP3 PlayerJonathan E. Scalera, Mark Jones. 319-320 [doi]
- Accelerating Embedded Applications using Dynamically Reconfigurable Hardware and Evolutionary AlgorithmsJim Harkin, T. Martin McGinnity, Liam P. Maguire. 321-322 [doi]
- Implementation of a Configurable Controller for an AC Drive Control: A Case StudyMaria Imecs, Péter Bikfalvi, Sergiu Nedevschi, József Vásárhelyi. 323-324 [doi]
- Pattern Recognition and Reconstruction on an FPGA Coprocessor BoardReinhard Männer, M. Sessler, Harald Simmler. 325-328 [doi]
- FCCMS and the Memory WallSteven Derrien, Sanjay V. Rajopadhye. 329-330 [doi]
- A C to Hardware/Software CompilerKia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh. 331-332 [doi]
- Evaluating Hardware Compilation TechniquesMarkus Weinhardt, Wayne Luk. 333-334 [doi]
- Adapting Constant Multipliers in a Neural Network ImplementationPhilip James-Roxby, Brandon Blodget. 335-336 [doi]
- A Networked FPGA-Based Hardware Implementation of a Neural Network ApplicationHéctor Fabio Restrepo, Ralph Hoffmann, Andrés Pérez-Uribe, Christof Teuscher, Eduardo Sanchez. 337-338 [doi]
- Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing SystemsKatsuharu Suzuki, Michael X. Wang, Zhao Fang, Wayne Wei-Ming Dai. 339-340 [doi]
- An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal ProcessingTim Courtney, Richard H. Turner, Roger Woods. 341-343 [doi]
- Combining Serialization and Reconfiguration for Convolver DesignsArran Derbyshire, Wayne Luk. 344-346 [doi]