Abstract is missing.
- Time-Critical Software Deceleration in an FCCMPhilip James-Roxby, Gordon J. Brebner, Dennis Bemmann. 3-12 [doi]
- Design Patterns for Reconfigurable ComputingAndré DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael C. Vanier, Michael G. Wrighton. 13-23 [doi]
- Virtual Memory Window for a Portable Reconfigurable Cryptography CoprocessorMiljan Vuletic, Laura Pozzi, Paolo Ienne. 24-33 [doi]
- Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAsDavid Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee. 37-46 [doi]
- PyGen: A MATLAB/Simulink Based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAsJingzhao Ou, Viktor K. Prasanna. 47-56 [doi]
- Automated Least-Significant Bit Datapath Optimization for FPGAsMark L. Chang, Scott Hauck. 59-67 [doi]
- An Arithmetic Library and Its Application to the N-body ProblemKuen Hung Tsoi, Chun Hok Ho, H. C. Yeung, Philip Heng Wai Leong. 68-78 [doi]
- Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point DesignsAltaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung. 79-88 [doi]
- A Dynamically-Reconfigurable, Power-Efficient Turbo DecoderJian Liang, Russell Tessier, Dennis Goeckel. 91-100 [doi]
- A Flexible Hardware Encoder for Low-Density Parity-Check CodesDong-U Lee, Wayne Luk, Connie Wang, Christopher Jones, Michael Smith, John D. Villasenor. 101-111 [doi]
- ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet SchedulersRaj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West. 115-124 [doi]
- Deep Packet Filter with Dedicated Logic and Read Only MemoriesYoung H. Cho, William H. Mangione-Smith. 125-134 [doi]
- A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAsZachary K. Baker, Viktor K. Prasanna. 135-144 [doi]
- Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time ApplicationsMiriam Leeser, Shawn Miller, Haiqian Yu. 147-155 [doi]
- FPGA-Based Acceleration of the 3D Finite-Difference Time-Domain MethodJames P. Durbano, Fernando E. Ortiz, John R. Humphrey, Petersen F. Curt, Dennis W. Prather. 156-163 [doi]
- Register Binding for FPGAs with Embedded MemoryHassan Al Atat, Iyad Ouaiss. 167-175 [doi]
- Defect and Fault Tolerance of Reconfigurable Molecular ComputingMehdi Baradaran Tahoori, Subhasish Mitra. 176-185 [doi]
- Communications Scheduling for Concurrent Processes on Reconfigurable ComputersMaya Gokhale, Christine Ahrens, Janette Frigo, Christophe Wolinski. 186-193 [doi]
- Reconfigurable Molecular Dynamics SimulatorNavid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow. 197-206 [doi]
- Accelerating Seismic Migration Using FPGA-Based Coprocessor PlatformHe Chuan, Mi Lu, Chuanwen Sun. 207-216 [doi]
- Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS PerformanceKeith D. Underwood, K. Scott Hemmert. 219-228 [doi]
- FPGA-Based Implementation of a Robust IEEE-754 Exponential UnitChristopher C. Doss, Robert L. Riley Jr.. 229-238 [doi]
- Design of an On-Line IEEE Floating-Point Addition Unit for FPGAsSteven D. Krueger, Peter-Michael Seidel. 239-246 [doi]
- Scalable Pattern Matching for High Speed NetworksChristopher R. Clark, David E. Schimmel. 249-257 [doi]
- Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern MatchingIoannis Sourdis, Dionisios N. Pnevmatikatos. 258-267 [doi]
- A Structured System Methodology for FPGA Based System-on-A-Chip DesignN. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk. 271-272 [doi]
- Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAsEmre Özer, Andy Nisbet, David Gregg. 273-274 [doi]
- Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-PathMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis. 275-276 [doi]
- Hardware-in-the-Loop Evolution of a 3-bit MultiplierGregory V. Larchev, Jason D. Lohn. 277-278 [doi]
- FPGA Montgomery Multiplier Architectures - A ComparisonCiaran McIvor, Máire McLoone, John V. McCanny. 279-282 [doi]
- Design Methodology of a Configurable System-on-Chip ArchitectureSebastian Wallner. 283-284 [doi]
- Word-Length Optimization of Folded Polynomial EvaluationGeorge A. Constantinides, Abunaser Miah, Nalin Sidahao. 285-286 [doi]
- Migrating Functionality from ROMS to Embedded MultipliersGareth W. Morris, George A. Constantinides, Peter Y. K. Cheung. 287-288 [doi]
- A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level ComputationDavid Wentzlaff, Anant Agarwal. 289-290 [doi]
- Validation of an Advanced Encryption Standard (AES) IP CoreValeri F. Tomashau, Tom Kean. 291-292 [doi]
- Unidirectional Switch-Boxes for Synthesizable Reconfigurable ArraysSami Khawam, Tughrul Arslan, Fred Westall. 293-295 [doi]
- The MOLEN Processor PrototypeGeorgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis. 296-299 [doi]
- FPGA Acceleration of Rigid Molecule InteractionsTom Van Court, Yongfeng Gu, Martin C. Herbordt. 300-301 [doi]
- A Single Program Multiple Data Parallel Processing Platform for FPGAsPhil James-Roxby, Paul R. Schumacher, Charlie Ross. 302-303 [doi]
- Hyperreconfigurable Architectures for Fast Run Time ReconfigurationSebastian Lange, Martin Middendorf. 304-305 [doi]
- A Generator of High-Speed Floating-Point ModulesGerardo Leyva, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz. 306-307 [doi]
- A 21.54 Gbits/s Fully Pipelined AES Processor on FPGAAlireza Hodjat, Ingrid Verbauwhede. 308-309 [doi]
- An FPGA Interpolation Processor for Soft-Decision Reed-Solomon DecodingWarren J. Gross, Frank R. Kschischang, P. Glenn Gulak. 310-311 [doi]
- Buffer Schemes for Runtime Reconfiguration of Function Variants in Communication SystemsDirk Eilers, Helmut Steckenbiller, Andreas Herkersdorf. 312-315 [doi]
- FPGA Based Network Intrusion Detection using Content Addressable MemoriesLong Bu, John A. Chandy. 316-317 [doi]
- Using FIFOs in Hardware-Software Co-Design for FPGA Based Embedded SystemsCharlie Ross, A. P. Wim Böhm. 318-319 [doi]
- A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image ProcessingJianchun Li, Christos A. Papachristou, Raj Shekhar. 320-321 [doi]
- Implementation Results of Bloom Filters for String MatchingMichael Attig, Sarang Dharmapurikar, John W. Lockwood. 322-323 [doi]
- An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed ArithmeticDaniel J. Allred, Walter Huang, Venkatesh Krishnan, Heejong Yoo, David V. Anderson. 324-325 [doi]
- Power Management for FPGAs: Power-Driven Design PartitioningRajarshi Mukherjee, Seda Ogrenci Memik. 326-327 [doi]
- Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable ProcessorNoriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima. 328-329 [doi]
- FPGA based Embedded Processing Architecture for the QRD-RLS AlgorithmDeepak Boppana, Kully Dhanoa, Jesse Kempa. 330-331 [doi]
- A Dataflow Control Unit for C-to-Configurable Pipelines Compilation FlowAndrea Cappelli, Andrea Lodi 0002, Claudio Mucci, Mario Toma, Fabio Campi. 332-333 [doi]
- Secure Remote Control of Field-programmable Network DevicesHaoyu Song, Jing Lu, John W. Lockwood, James Moscola. 334-335 [doi]
- An Alternate Wire Database for Xilinx FPGAsNeil Steiner, Peter M. Athanas. 336-337 [doi]
- Duty Cycle Aware Application Design using FPGAsSumit Mohanty, Viktor K. Prasanna. 338-339 [doi]
- Automating the Layout of Reconfigurable Subsystems Via Template ReductionShawn Phillips, Akshay Sharma, Scott Hauck. 340-341 [doi]
- Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual MachineMatthias Dyer, Marco Platzner, Lothar Thiele. 342-344 [doi]