Abstract is missing.
- Kiwi: Synthesis of FPGA Circuits from Parallel ProgramsDavid J. Greaves, Satnam Singh. 3-12 [doi]
- Hardware Scripting in GelJonathan Bachrach, Dany Qumsiyeh, Mark Tobenkin. 13-22 [doi]
- Performance Analysis with High-Level Languages for High-Performance Reconfigurable ComputingJohn Curreri, Seth Koehler, Brian Holland, Alan D. George. 23-30 [doi]
- A SRAM-based Architecture for Trie-based IP Lookup Using FPGAHoang Le, Weirong Jiang, Viktor K. Prasanna. 33-42 [doi]
- A Scalable High Throughput Firewall in FPGAGajanan S. Jedhe, Arun Ramamoorthy, Kuruvilla Varghese. 43-52 [doi]
- A Memory-Efficient FPGA-based Classification EngineAntonis Nikitakis, Ioannis Papaefstathiou. 53-62 [doi]
- The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA ReconfigurationShannon Koh, Oliver Diessel. 65-76 [doi]
- Autonomous System on a Chip Adaptation through Partial Runtime ReconfigurationMatthew French, Erik Anderson, Dong-In Kang. 77-86 [doi]
- Scheduling Intervals for Reconfigurable ComputingWenyin Fu, Katherine Compton. 87-96 [doi]
- DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAsSaar Drimer, Tim Güneysu, Christof Paar. 99-108 [doi]
- High-Speed Elliptic Curve Cryptography Accelerator for Koblitz CurvesKimmo U. Järvinen, Jorma O. Skyttä. 109-118 [doi]
- An FPGA Implementation of Explicit-State Model CheckingMary Ellen Fuess, Miriam Leeser, Tim Leonard. 119-126 [doi]
- Power-Aware and Branch-Aware Word-Length OptimizationWilliam G. Osborne, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer. 129-138 [doi]
- Simultaneous Retiming and Placement for Pipelined NetlistsKenneth Eguro, Scott Hauck. 139-148 [doi]
- Map-reduce as a Programming Model for Custom Computing MachinesJackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, Bill S. H. Kwan, Chris C. C. Cheung, Anthony P. C. Chan, Philip Heng Wai Leong. 149-159 [doi]
- FPGA-Based Co-processor for Singular Value Array Reconciliation TomographyJack Coyne, David Cyganski, R. James Duckworth. 163-172 [doi]
- Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison StudyJeff Chase, Brent E. Nelson, John Bodily, Zhaoyi Wei, Dah-Jye Lee. 173-182 [doi]
- Multiobjective Optimization of FPGA-Based Medical Image RegistrationOmkar Dandekar, William Plishker, Shuvra S. Bhattacharyya, Raj Shekhar. 183-192 [doi]
- Scaling Soft Processor SystemsMartin Labrecque, Peter Yiannacouras, J. Gregory Steffan. 195-205 [doi]
- Reconfigurable Work Farms on a Massively Parallel Processor ArrayMichael Butts, Brad Budlong, Paul Wasson, Ed White. 206-215 [doi]
- Titan-R: A Reconfigurable Hardware Implementation of a High-Speed CompressorKonstantinos Papadopoulos, Ioannis Papaefstathiou. 216-225 [doi]
- Credit Risk Modelling using Hardware Accelerated Monte-Carlo SimulationDavid B. Thomas, Wayne Luk. 229-238 [doi]
- Sparse Matrix-Vector Multiplication on a Reconfigurable SupercomputerDavid DuBois, Andrew DuBois, Carolyn Connor Davenport, Steve Poole. 239-247 [doi]
- An Efficient O(1) Priority Queue for Large FPGA-Based Discrete Event Simulations of Molecular DynamicsMartin C. Herbordt, Francois Kosie, Josh Model. 248-257 [doi]
- Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA PlatformsSven-Ole Voigt, Thomas Teufel. 261-262 [doi]
- Improving Performance of Partial Reconfiguration Using Strategy of Virtual DeletionTian Hangpei, Deyuan Gao, Wei Wu, Xiaoya Fan, Zhu Yian. 263-264 [doi]
- ShareStreams-V: A Virtualized QoS Packet Scheduling AcceleratorKangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan. 265-268 [doi]
- An Extensible I/O SubsystemBharat Sukhwani, Alessandro Forin, Richard Neil Pittman. 269-270 [doi]
- Multi-stage Pipelining MD5 Implementations on FPGA with Data ForwardingAnh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi. 271-272 [doi]
- MPLEM: An 80-processor FPGA Based Multiprocessor SystemGeorgios-Grigorios Mplemenos, Ioannis Papaefstathiou. 273-274 [doi]
- An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed InterconnectsHanyu Liu, Xiaolei Chen, Yajun Ha. 275-276 [doi]
- SMILE: Scientific Parallel Multiprocessing based on Low-Cost Reconfigurable HardwareEmilio Castillo, Cesar Pedraza, Javier Castillo, Cristobal Camarero, José Luis Bosque, Rafael Menéndez de Llano, José I. Martínez. 277-278 [doi]
- Reconfigurable Constraint Repetition Unit for Regular Expression MatchingMiad Faezipour, Mehrdad Nourani. 279-280 [doi]
- Fast Multivariate Signature Generation in Hardware: The Case of RainbowSundar Balasubramanian, Andrey Bogdanov, Andy Rupp, Jintai Ding, Harold W. Carter. 281-282 [doi]
- Configurable Flow Models for FPGA Particle Graphics EnginesAndrew J. Wong, Warren J. Gross. 283-284 [doi]
- Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPHHayden Kwok-Hay So, Robert W. Brodersen. 285-286 [doi]
- Efficient Reconfigurable On-Chip Buses for FPGAsDirk Koch, Christian Haubelt, Jürgen Teich. 287-290 [doi]
- Investigation of Programming Models for Emerging FPGA-Based High Performance Computing SystemsAndrew W. H. House, Paul Chow. 291-292 [doi]
- Hardware Compilation from Machine Code with M2VKarl Meier, Alessandro Forin. 293-295 [doi]
- An Implementation of the Conjugate Gradient Algorithm on FPGAsDavid DuBois, Andrew DuBois, Thomas Boorman, Carolyn Connor, Steve Poole. 296-297 [doi]
- FPGA Session Control (FSC): Providing Remote Access to a Cluster of FPGAsYamuna Rajasekhar, Yashodhan Phatak, Andrew G. Schmidt, William V. Kritikos, Ron Sass. 298-299 [doi]
- Reconfigurable Computing Cluster Project: Phase I BriefAndrew G. Schmidt, William V. Kritikos, Siddhartha Datta, Ron Sass. 300-301 [doi]
- Scalable and Portable Architecture for Probability Density Function Estimation on FPGAsKarthik Nagarajan, Brian Holland, K. Clint Slatton, Alan D. George. 302-303 [doi]
- A Hardware Efficient Support Vector Machine Architecture for FPGAKevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Aman Gayasen. 304-305 [doi]
- Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array ArchitecturesChristophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig. 306-309 [doi]
- Matrix Computations on Heterogeneous Reconfigurable SystemsLing Zhuo, Qingbo Wang, Viktor K. Prasanna. 310-311 [doi]
- System Level Design Methodology for Hybrid Multi-Processor SoC on FPGAJason Wu, John W. Williams, Neil Bergmann. 312-313 [doi]
- A New Powerful Scalable Generic Multi-Standard LDPC Decoder ArchitectureFrançois Charot, Christophe Wolinski, Nicolas Fau, François Hamon. 314-315 [doi]
- An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable HardwareSherman Braganza, Miriam Leeser. 316-317 [doi]
- Facilitating Processor-Based DPR Systems for non-DPR ExpertsEdward Chen, William A. Gruver, Dorian Sabaz, Lesley Shannon. 318-319 [doi]
- Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable ArchitecturesCarlos Morra, João Bispo, João M. P. Cardoso, Jürgen Becker. 320-321 [doi]