Abstract is missing.
- VLSI architectures for field programmable gate arrays: a case studyRoger Woods, A. Cassidy, J. Gray. 2-9 [doi]
- Assessing document relevance with run-time reconfigurable machinesBernard K. Gunther, George Milne, Lakshmi Narasimhan. 10-17 [doi]
- Using MORRPH in an industrial machine vision systemWilliam E. King IV, Thomas H. Drayer, Richard W. Conners, Philip A. Araman. 18-26 [doi]
- A software development system for FPGA-based data acquisition systemsAlan S. Wenban, Geoffrey Brown. 28-37 [doi]
- Bit-serial pipeline synthesis for multi-FPGA systems with C++ design captureTsuyoshi Isshiki, Wayne Wei-Ming Dai. 38-47 [doi]
- Revisiting Smalltalk-80 blocks: a logic generator for FPGAsBernard Pottier, José-Luis Llopis. 48-57 [doi]
- RACER: a reconfigurable constraint-length 14 Viterbi decoderDavid Yeh, Gennady Feygin, Paul Chow. 60-69 [doi]
- Configurable computing solutions for automatic target recognitionJohn D. Villasenor, Brian Schoner, Kang-Ngee Chia, Charles Zapata, Hea Joung Kim, Christopher R. Jones 0001, Shane Lansing, Bill Mangione-Smith. 70-79 [doi]
- Exploring architectures for volume visualization on the Teramac custom computerW. Bruce Culbertson, Rick Amerson, Richard J. Carter, Philip Kuekes, Greg Snider. 80-88 [doi]
- Using rapid prototyping to teach the design of complete computing solutionsPeter M. Athanas, Rhett D. Hudson. 90-97 [doi]
- Aizup-a pipelined processor design and implementation on XILINX FPGA chipYamin Li, Wanming Chu. 98-106 [doi]
- Implementation of IEEE single precision floating point addition and multiplication on FPGAsLoucas Louca, Todd A. Cook, William H. Johnson. 107-116 [doi]
- Mixing fixed and reconfigurable logic for array processingPieter J. Bakkes, Jan J. Du Plessis, Brad L. Hutchings. 118-125 [doi]
- OneChip: an FPGA processor with reconfigurable logicRalph Wittig, Paul Chow. 126-135 [doi]
- A PCI-compatible FPGA-coprocessor for 2D/3D image processingGünter Knittel. 136-145 [doi]
- SOP: a reconfigurable massively parallel system and its control-data-flow based compiling methodTsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara. 148-156 [doi]
- MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resourcesEthan Mirsky, André DeHon. 157-166 [doi]
- Modelling and optimising run-time reconfigurable systemsWayne Luk, Nabeel Shirazi, Peter Y. K. Cheung. 167-176 [doi]
- Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architecturesJames B. Peterson, Brendan O'Connor, Peter M. Athanas. 178-187 [doi]
- Expressing dynamic reconfiguration by partial evaluationSatnam Singh, Jonathan Hogg, Derek McAuley. 188-194 [doi]
- Supporting FPGA microprocessors through retargetable software toolsDavid A. Clark, Brad L. Hutchings. 195-203 [doi]
- On the viability of FPGA-based integrated coprocessorsOsama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke. 206-215 [doi]
- Genetic algorithms in software and in hardware-a performance analysis of workstation and custom computing machine implementationsPaul S. Graham, Brent E. Nelson. 216-225 [doi]
- A quantitative analysis of processor-programmable logic interfaceSriram K. Rajamani, Pramod Viswanath. 226-234 [doi]