Table of Contents

• Evaluating the Performance Efficiency of a Soft-Processor, Variable-Length, Parallel-Execution-Unit Architecture for FPGAs Using the RISC-V ISAEric Matthews, Zavier Aguila, Lesley Shannon. 1-8 [doi]
• ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGAZhenyuan Ruan, Tong He, Bojie Li, Peipei Zhou, Jason Cong. 9-16 [doi]
• Hoplite-Q: Priority-Aware Routing in FPGA Overlay NoCsSiddhartha 0001, Nachiket Kapre. 17-24 [doi]
• A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-ChipShivukumar B. Patil, Tianqi Liu, Russell Tessier. 25-28 [doi]
• Improved Lightweight Implementations of CAESAR Authenticated CiphersFarnoud Farahmand, William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj. 29-36 [doi]
• High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA PlatformsWeikang Qiao, Jieqiong Du, Zhenman Fang, Michael Lo, Mau-Chung Frank Chang, Jason Cong. 37-44 [doi]
• FPGA Side Channel Attacks without Physical AccessChethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sébastien Pillement, Daniel Holcomb, Russell Tessier. 45-52 [doi]
• Inheriting Software Security Policies within Hardware IP ComponentsFestus Hategekimana, Joel Mandebi Mbongue, Md Jubaer Hossain Pantho, Christophe Bobda. 53-56 [doi]
• ReBNet: Residual Binarized Neural NetworkMohammad Ghasemzadeh 0002, Mohammad Samragh, Farinaz Koushanfar. 57-64 [doi]
• FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial NetworksAmir Yazdanbakhsh, Michael Brzozowski, Behnam Khaleghi, Soroush Ghodrati, Kambiz Samadi, Nam Sung Kim, Hadi Esmaeilzadeh. 65-72 [doi]
• Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAsPhilip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis. 73-80 [doi]
• FPDeep: Acceleration and Load Balancing of CNN Training on FPGA ClustersTong Geng, Tianqi Wang, Ahmed Sanaullah, Chen Yang, Rui Xu, Rushi Patel, Martin C. Herbordt. 81-84 [doi]
• Hot & Spicy: Improving Productivity with Python and HLS for FPGAsSam Skalicky, Joshua S. Monson, Andrew G. Schmidt, Matthew French. 85-92 [doi]
• Understanding Performance Differences of FPGAs and GPUsJason Cong, Zhenman Fang, Michael Lo, HanRui Wang, Jingxian Xu, Shaochong Zhang. 93-96 [doi]
• High-Frequency Absorption-FIFO Pipelining for Stratix 10 HyperFlexMadison N. Emas, Austin Baylis, Greg Stitt. 97-100 [doi]
• Concurrency-Aware Thread Scheduling for High-Level SynthesisNadesh Ramanathan, George A. Constantinides, John Wickerson. 101-108 [doi]
• High-Level Synthesis of FPGA Circuits with Multiple Clock DomainsOmar Ragheb, Jason Helge Anderson. 109-116 [doi]
• LegUp-NoC: High-Level Synthesis of Loops with Indirect AddressingAsif Islam, Nachiket Kapre. 117-124 [doi]
• Latte: Locality Aware Transformation for High-Level SynthesisJason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou. 125-128 [doi]
• Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine LearningSteve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang. 129-132 [doi]
• RapidWright: Enabling Custom Crafted Implementations for FPGAsChris Lavin, Alireza Kaviani. 133-140 [doi]
• Improving the Effectiveness of TMR Designs on FPGAs with SEU-Aware Incremental PlacementMatthew Cannon, Andrew Keller, Michael Wirthlin. 141-148 [doi]
• Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQJeffrey Goeders, Tanner Gaskin, Brad L. Hutchings. 149-156 [doi]
• HODS: Hardware Object Deserialization Inside SSD StorageDongyang Li, Fei Wu 0005, Yang Weng, Qing Yang, Changsheng Xie. 157-164 [doi]
• CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA PlatformsLiang Feng, Sharad Sinha, Wei Zhang, Yun Liang 0001. 165-172 [doi]
• Microscope on Memory: MPSoC-Enabled Computer Memory System AssessmentsAbhishek Kumar Jain, G. Scott Lloyd, Maya Gokhale. 173-180 [doi]
• FPGA-Based Real-Time Super-Resolution System for Ultra High Definition VideosZhuolun He, Hanxian Huang, Ming Jiang 0001, Yuanchao Bai, Guojie Luo. 181-188 [doi]
• OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured MeshesTobias Kenter, Gopinat Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt 0003, Ayesha Afzal, Frank Hannig, Jens Förstner, Christian Plessl. 189-196 [doi]
• A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback DatapathMakoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise. 197-204 [doi]
• EM-Aware Memory Mapping Algorithms for SRAM Based FPGAZhong Guan. 205 [doi]
• SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA SequencingJason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu. 206 [doi]
• PQ-CNN: Accelerating Product Quantized Convolutional Neural Network on FPGAJialiang Zhang, Jing Li. 207 [doi]
• NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing OverheadsGuohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek. 208 [doi]
• Exploiting Box Expansion and Grid Partitioning for Parallel FPGA RoutingMinghua Shen, Guojie Luo, Nong Xiao. 209 [doi]
• AccDNN: An IP-Based DNN Generator for FPGAsXiaofan Zhang, Junsong Wang, Chao Zhu, Yonghua Lin, Jinjun Xiong, Wen-mei W. Hwu, Deming Chen. 210 [doi]
• Reloc - An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration TilesBjorn Gottschall, Thomas PreuBer, Akash Kumar. 211 [doi]
• From C to Fault-Tolerant FPGA-Based SystemsDimitris Agiakatsikas, Ganghee Lee, Thomas Mitchell, Ediz Cetin, Oliver Diessel. 212 [doi]
• Wibheda: Framework for Data Dependency-Aware Multi-Constrained Hardware-Software Partitioning in FPGA-Based SoCs for IoT DevicesDeshya Wijesundera, Alok Prakash, Thilina Perera, Kalindu Herath, Thambipillai Srikanthan. 213 [doi]
• High-Speed Regular Expression Matching with Pipelined Memory-Based AutomataDenis Matousek, Jirí Matousek, Jan Korenek. 214 [doi]
• Rethinking Secure FPGAs: Towards a Cryptography-Friendly Configurable Cell Architecture and Its Automated Design FlowNele Mentens, Edoardo Charbon, Francesco Regazzoni. 215 [doi]
• A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid MediaAbdul-Amir Yassine, Yasmin Afsharnejad, Omar Ragheb, Vaughn Betz, Paul Chow. 216 [doi]
• Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube ComputerMd Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews, Marjan Asadinia. 217 [doi]
• Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGASunwoong Kim, Rob A. Rutenbar. 218 [doi]
• High Performance Dynamic Communication on Reconfigurable ClustersJiayi Sheng, Chen Yang, Tianqi Wang, Martin C. Herbordt. 219 [doi]
• Performance Prediction for Large-Scale Heterogeneous PlatformsRyota Yasudo, Ana Lucia Varbanescu, José Gabriel F. Coutinho, Wayne Luk, Hideharu Amano. 220 [doi]
• Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduceKatayoun Neshatpour, Hosein Mohammadi Makrani, Avesta Sasan, Hassan Ghasemzadeh, Setareh Rafatirad, Houman Homayoun. 221 [doi]
• Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible TrinomialsJosé Luis Imaña. 222 [doi]
• A PYNQ-Based Framework for Rapid CNN PrototypingErwei Wang, James J. Davis, Peter Y. K. Cheung. 223 [doi]
• Automatic Offloading of Cluster AcceleratorsCiro Ceissler, Ramon Nepomuceno, Marcio Machado Pereira, Guido Araujo. 224 [doi]
• Cross Component Optimization for Modern LTE Downlink Shared Channel ImplementationJieming Xu, Miriam Leeser. 225 [doi]
• Bridging the Gap between Advanced Memory and Heterogeneous ArchitecturesAbhi D. R., Ron Sass, Andrew G. Schmidt, Matthew French. 226 [doi]
• Acceleration Framework for FPGA Implementation of OpenVX Graph PipelinesSajjad Taheri, Jin Heo, Payman Behnam, Jeffrey Chen, Alexander V. Veidenbaum, Alexandru Nicolau. 227 [doi]
• Automatic Interior I/O Elimination in Systolic Array ArchitectureJason Cong, Jie Wang. 228 [doi]