Table of Contents

• XBERT: Xilinx Logical-Level Bitstream Embedded RAM TransfusionMatthew Hofmann, Zhiyao Tang, Jonathan Orgill, Jonathan Nelson, David Glanzman, Brent Nelson, André DeHon. 1-9 [doi]
• A Safari through FPGA-based Neural Network Compilation and Design Automation FlowsPatrick Plagwitz, Frank Hannig, Martin Ströbel, Christoph Strohmeyer, Jürgen Teich. 10-19 [doi]
• Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAsDaniel Holanda Noronha, Zhiqiang Que, Wayne Luk, Steven J. E. Wilton. 20-28 [doi]
• BoostGCN: A Framework for Optimizing GCN Inference on FPGABingyi Zhang, Rajgopal Kannan, Viktor K. Prasanna. 29-39 [doi]
• FA-LAMP: FPGA-Accelerated Learned Approximate Matrix Profile for Time Series Similarity PredictionAmin Kalantar, Zachary Zimmerman, Philip Brisk. 40-49 [doi]
• HAO: Hardware-aware Neural Architecture Optimization for Efficient InferenceZhen Dong, Yizhao Gao, Qijing Huang 0001, John Wawrzynek, Hayden K. H. So, Kurt Keutzer. 50-59 [doi]
• GAME: Gaussian Mixture Model Mapping and Navigation Engine on Embedded FPGAYuanfan Xu, Zhaoliang Zhang, Jincheng Yu, Jianfei Cao, Haolin Dong, Zhengfeng Huang, Yu Wang 0002, Huazhong Yang. 60-68 [doi]
• Systematically migrating an operational microphysics parameterisation to FPGA technologyJames Stanley Targett, Wayne Luk, Michael Lange 0001, Olivier Marsden. 69-77 [doi]
• Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA DesignFrancesco Sgherzi, Alberto Parravicini, Marco Siracusa, Marco D. Santambrogio. 78-87 [doi]
• Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAsXiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das. 88-96 [doi]
• GORDON: Benchmarking Optane DC Persistent Memory Modules on FPGAsJialiang Zhang, Nicholas Beckwith, Jing Jane Li. 97-105 [doi]
• FANS: FPGA-Accelerated Near-Storage SortingWeikang Qiao, Jihun Oh, Licheng Guo, Mau-Chung Frank Chang, Jason Cong. 106-114 [doi]
• Mocarabe: High-Performance Time-Multiplexed Overlays for FPGAsFrederick Tombs, Alireza Mellat, Nachiket Kapre. 115-123 [doi]
• HEDAcc: FPGA-based Accelerator for High-order Epistasis DetectionGaspar Ribeiro, Nuno Neves, Sergio Santander-Jiménez, Aleksandar Ilic. 124-132 [doi]
• The Importance of Being X-Drop: High Performance Genome Alignment on Reconfigurable HardwareAlberto Zeni, Guido Walter Di Donato, Lorenzo Di Tucci, Marco Rabozzi, Marco D. Santambrogio. 133-141 [doi]
• Upgrade of FPGA Range-Limited Molecular Dynamics to Handle Hundreds of ProcessorsChunshu Wu, Tong Geng, Sahan Bandara, Chen Yang 0010, Vipin Sachdeva, Woody Sherman, Martin C. Herbordt. 142-151 [doi]
• FPGA-accelerated Iterative Reconstruction for Transmission Electron TomographyLinjun Qiao, Guojie Luo, Wentai Zhang 0001, Ming Jiang 0001. 152-156 [doi]
• Optimized FPGA-based Deep Learning Accelerator for Sparse CNN using High Bandwidth MemoryChao Jiang, David Ojika, Bhavesh Patel, Herman Lam. 157-164 [doi]
• unzipFPGA: Enhancing FPGA-based CNN Engines with On-the-Fly Weights GenerationStylianos I. Venieris, Javier Fernández-Marqués, Nicholas D. Lane. 165-175 [doi]
• ESCA: Event-Based Split-CNN Architecture with Data-Level Parallelism on UltraScale+ FPGAPankaj Bhowmik, Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda. 176-180 [doi]
• 3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGAHuipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu. 181-185 [doi]
• Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAsDillon Huff, Steve Dai, Pat Hanrahan. 186-194 [doi]
• Probabilistic Scheduling in High-Level SynthesisJianyi Cheng, John Wickerson, George A. Constantinides. 195-203 [doi]
• Extending High-Level Synthesis for Task-Parallel ProgramsYuze Chi, Licheng Guo, Jason Lau, Young Kyu Choi, Jie Wang 0022, Jason Cong. 204-213 [doi]
• HLS-Compatible, Embedded-Processor Stream LinksEric Micallef, Yuanlong Xiao, André DeHon. 214-218 [doi]
• An Empirical Study of the Reliability of High-Level Synthesis ToolsYann Herklotz, Zewei Du, Nadesh Ramanathan, John Wickerson. 219-223 [doi]
• Cloud FPGA Cartography using PCIe ContentionShanquan Tian, Ilias Giechaskiel, Wenjie Xiong 0001, Jakub Szefer. 224-232 [doi]
• Trusted Configuration in Cloud FPGAsShaza Zeitouni, Jo Vliegen, Tommaso Frassetto, Dirk Koch, Ahmad-Reza Sadeghi, Nele Mentens. 233-241 [doi]
• Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAsShanquan Tian, Shayan Moini, Adam Wolnikowski, Daniel E. Holcomb, Russell Tessier, Jakub Szefer. 242-246 [doi]
• Runtime Detection of Probing/Tampering on Interconnecting BusesZhenyu Xu, Thomas Mauldin, Qing Yang, Tao Wei. 247-251 [doi]
• A General Video Processing Framework on Edge Computing FPGAsFeng Yu, He Li, Rongshi Dai, Yongming Tang. 252 [doi]
• A Tunable Dual-Edge Time-to-Digital ConverterColin Drewes, Steven Harris, Winnie Wang, Richard Appen, Olivia Weng, Ryan Kastner, William Hunter, Christopher McCarty, Dustin Richmond. 253 [doi]
• Accelerating Large-Scale Nearest Neighbor Search with Computational Storage DeviceJi-Hoon Kim, Yeo-Reum Park, Jaeyoung Do, Soo Young Ji, Joo-Young Kim. 254 [doi]
• ARC: Reconfigurable Cache Security Assurance with Application-Specific Randomized Mapping in FPGA-Based Heterogeneous ComputingSanjay Gandham, Rakin Muhammad Shadab, Mingjie Lin. 255 [doi]
• AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA DesignYanze Li, Yufan Zhang, Jiafeng Liu, Jian Wang, Jinmei Lai, Gang Qu. 256 [doi]
• Configurable Pipelined Datapath for Data Acquisition in Interventional Computed TomographyDaniele Passaretti, Thilo Pionteck. 257 [doi]
• DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA TransfersJan Kubálek, Jakub Cabal, Martin Spinler, Radek Isa. 258 [doi]
• Edge Accelerator for Lifelong Deep Learning using Streaming Linear Discriminant AnalysisDuvindu Piyasena, Siew Kei Lam, Meiqing Wu. 259 [doi]
• Enabling OpenMP Task Parallelism on Multi-FPGAsRamon Nepomuceno, Renan Sterle, Guilherme Valarini, Marcio Machado Pereira, Hervé Yviquel, Guido Araujo. 260 [doi]
• Extending HLS with High-Level Descriptive Language for Configurable Algorithm-Level Spatial Structure DesignChengyue Wang, Sitao Huang, Wen-mei Hwu, Deming Chen. 261 [doi]
• FERMAT: FPGA-Accelerated Heterogeneous Computing Platform Near NVMe StorageYu Zou, Mingjie Lin. 262 [doi]
• FFIVE: An FPGA Framework for Interactive VNF EnvironmentsJuan Camilo Vega, Mohammad Ewais, Alberto Leon-Garcia, Paul Chow. 263 [doi]
• Heterogeneous Dual-Core Overlay Processor for Light-Weight CNNsTiandong Zhao, Yunxuan Yu, Kun Wang, Lei He. 264 [doi]
• Near-Storage Acceleration of Database Query Processing with SmartSSDsMohammadreza Soltaniyeh, Veronica Lagrange Moutinho dos Reis, Matthew Bryson, Richard P. Martin, Santosh Nagarakatte. 265 [doi]
• NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational LogicMahdi Nazemi, Arash Fayyazi, Amirhossein Esmaili, Atharva Khare, Soheil Nazar Shahsavani, Massoud Pedram. 266-267 [doi]
• ONT-X: An FPGA Approach to Real-time Portable Genomic AnalysisC. N. Ramachandra, Anirban Nag, Rajeev Balasubramonion, Gurpreet S. Kalsi, Kamlesh R. Pillai, Sreenivas Subramoney. 268-269 [doi]
• Particle Mesh Ewald for Molecular Dynamics in OpenCL on an FPGA ClusterLawrence C. Stewart, Carlo Pascoe, Emery Davis, Brian W. Sherman, Martin C. Herbordt, Vipin Sachdeva. 270 [doi]
• Pharos: a Performance Monitor for Multi-FPGA SystemsArzhang Rafii, Paul Chow, Welson Sun. 271 [doi]
• Reconfigurable Synthesizable Synchronization FIFOsAmeer M. S. Abdelhadi, He Li. 272 [doi]
• Scalable FPGA Median Filtering via a Directional Median CascadeOscar Rahnama, Stuart Golodetz, Tommaso Cavallari, Philip H. S. Torr. 273 [doi]
• Scheduling Persistent and Fully Cooperative InstructionsYu Yang, Ahmed Hemani, Kolin Paul. 274 [doi]
• TOCO: A Systolic Network for Efficient Transposed Convolutions with Output-Reuse PathsZhengzheng Ma, Guojie Luo. 275 [doi]
• TwinDNN: A Tale of Two Deep Neural NetworksHyunmin Jeong, Deming Chen. 276 [doi]
• Using hls4ml to Map Convolutional Neural Networks on Interconnected FPGA DevicesEvangelos Mageiropoulos, Nikolaos Chrysos, Nikolaos Dimou, Manolis Katevenis. 277 [doi]
• An FPGA Based Hardware Accelerated Framework for Solar Spectra Matching with Parameterized Matched Filter IP CoreVerjina Torosian Khouygani, Shahnam Mirzaei, Christian Beck, Debi Prasad Choudhary. 278 [doi]
• Time-Domain FPGA Power Delivery Network Characterization MethodologyYanran P. Chen, Martin L. Voogel, Ed Priest, Qian Wang, Ranjeeth Doppalapudi, Praful Jain. 279 [doi]