Abstract is missing.
- Enabler-based synchronizer model for clock domain crossing static verificationM. Kebaili, Katell Morin-Allory, J. C. Brignone, D. Borrione Mejid Kebaili, Jean-Christophe Brignone, Katell Morin-Allory, Dominique Borrione. 11-17 [doi]
- Temporal decoupling with error-bounded predictive quantum controlGeorg Gläser, Gregor Nitsche, Eckhard Hennig. 18-23 [doi]
- A methodology for inserting clock-management strategies in transaction-level models of systemon- chipsHend Affes, Michel Auguin, François Verdier, Alain Pegatoquet. 24-30 [doi]
- Modeling power consumption at system-level for design of power integrity-aware AMS-circuitsXiao Pan, Javier Moreno Molina, Christoph Grimm 0001. 32-39 [doi]
- WiSeBat: accurate energy benchmarking of wireless sensor networksQuentin Bramas, Wilfried Dron, Mariem Ben Fadhl, Khalil Hachicha, Patrick Garda, Sébastien Tixeuil. 40-47 [doi]
- Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interfaceRobert Lajos Bücs, Luis Gabriel Murillo, Ekaterina Korotcenko, Gaurav Dugge, Rainer Leupers, Gerd Ascheid, Andreas Ropers, Markus Wedler, Andreas Hoffmann. 49-56 [doi]
- Standard compliant co-simulation models for verification of automotive embedded systemsMartin Krammer, Helmut Martin, Zoran Radmilovic, Simon Erker, Michael Karner. 57-64 [doi]
- Conservative behavioural modelling in systemc-AMSSara Vinco, Michele Lora, Mark Zwolinski. 65-72 [doi]
- A special-purpose language for implementing pipelined FPGA-based acceleratorsCristiano Bacelar de Oliveira, Ricardo Menotti, João M. P. Cardoso, Eduardo Marques. 74-81 [doi]
- Towards a toolchain for assertion-driven test sequence generationLaurence Pierre. 82-89 [doi]
- Architectural system modeling for correct-by-construction RTL designJoakim Urdahl, Dominik Stoffel, Wolfgang Kunz. 90-97 [doi]
- Extensions to the UML profile for MARTE for distributed embedded systemsEmad Samuel Malki Ebeid, Julio L. Medina, Davide Quaglia, Franco Fummi. 99-106 [doi]
- Building a dynamically reconfigurable system through a high development flowDavid de la Fuente, Jesús Barba, Xerach Peña, Juan Carlos López, Pablo Peñil, Pablo Pedro Sanchez. 107-114 [doi]
- Mixed-criticality system modelling with dynamic execution mode switchingPhilipp Ittershagen, Kim Grüttner, Wolfgang Nebel. 116-121 [doi]
- Enhancing analysability and time predictability in UML/MARTE component-based application modelsFernando Herrera, Pablo Peñil, Eugenio Villar. 122-129 [doi]
- Temporal independence validation of an IEC-61508 compliant mixed-criticality system based on multicore partitioningAsier Larrucea, Irune Agirre, Carlos Fernando Nicolas, Jon Perez, Mikel Azkarate-askasua, Ton Trapman. 130-137 [doi]