Abstract is missing.
- Symbolic Trajectory EvaluationScott Hazelhurst, Carl-Johan H. Seger. 3-78
- Verification with Abstract State Machines Using MDGsEduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Zijian Zhou. 79-113
- Design Verification Using Synchronized TransitionsJørgen Staunstrup. 114-155
- Hardware Verification Using PVSMandayam K. Srivas, Harald Rueß, David Cyrluk. 156-205
- Verifying VHDL Designs with COSPANKathi Fisler, Robert P. Kurshan. 206-247
- The C@S SystemKlaus Schneider, Thomas Kropf. 248-329
- Appendix: The Common Book ExamplesThomas Kropf. 330-367