Abstract is missing.
- A reconfigurable futurePhil Bishop, Chris Sullivan. 2-7 [doi]
- Seamless top-down flow for quick trial of HW/SW co-designNaotoshi Nojiri, Tadatoshi Ishii. 8-12 [doi]
- Networking on chip with platform FPGAsGordon J. Brebner, Delon Levi. 13-20 [doi]
- FPGA-based high-speed emulator of quantum computingMinoru Fujishima. 21-26 [doi]
- High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applicationsRiad Stefo, Jörg Schreiter, Jens-Uwe Schluessler, René Schüffny. 28-34 [doi]
- Improved SVD systolic array and implementation on FPGAAziz Ahmedsaid, Abbes Amira, Ahmed Bouridane. 35-42 [doi]
- An implementation of the Rijndael on Async-WASMIIYoshinori Adachi, Kenichiro Ishikawa, Satoshi Tsutsumi, Hideharu Amano. 44-51 [doi]
- Modular exponentiation using parallel multipliersS.-H. Tang, K. S. Tsui, Philip Heng Wai Leong. 52-59 [doi]
- Implementation of Elliptic Curve Cryptosystems on a reconfigurable computerNghi Nguyen, Kris Gaj, David Caliga, Tarek A. El-Ghazawi. 60-67 [doi]
- A pattern-matching co-processor for network intrusion detection systemsChristopher R. Clark, David E. Schimmel. 68-74 [doi]
- A parallel look-up logarithmic number system addition/subtraction scheme for FPGABarry Lee, Neil Burgess. 76-83 [doi]
- Arbitrary function approximation in HDLs with application to the N-body problemChun Hok Ho, Kuen Hung Tsoi, H. C. Yeung, Yuet Ming Lam, Kin-Hong Lee, Philip Heng Wai Leong, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner. 84-91 [doi]
- Hierarchical segmentation schemes for function evaluationDong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung. 92-99 [doi]
- FPGA implementations of fast fourier transforms for real-time signal and image processingIsa Servan Uzun, Abbes Amira, Ahmed Bouridane. 102-109 [doi]
- An FPGA-based re-configurable 24-bit 96kHz sigma-delta audio DACRay C. C. Cheung, Kong-Pang Pun, Steve C. L. Yuen, Kuen Hung Tsoi, Philip Heng Wai Leong. 110-117 [doi]
- Reconfiguration requirements for high speed wireless communication systemsThilo Pionteck, Lukusa D. Kabulepa, Clemens Schlachta, Manfred Glesner. 118-125 [doi]
- An FPGA implementation of Kak's instantaneously-trained, Fast-Classification neural networksJihan Zhu, Peter Sutton. 126-133 [doi]
- Concept and implementation of run-time resource management system operating on autonomously reconfigurable architectureYoshiki Nakane, Kouichi Nagami, Tsunemichi Shiozawa, Akira Nagoya. 136-143 [doi]
- High-level language extensions for run-time reconfigurable systemsT. K. Lee, Arran Derbyshire, Wayne Luk, Peter Y. K. Cheung. 144-151 [doi]
- Placement and routing for FPGA architectures supporting wide shallow memoriesSteven W. Oldridge, Steven J. E. Wilton. 154-161 [doi]
- Product-term based synthesizable embedded programmable logic coresAndy Yan, Steven J. E. Wilton. 162-169 [doi]
- An architecture for asynchronous FPGAsCatherine G. Wong, Alain J. Martin, Peter Thomas. 170-177 [doi]
- Evaluation of network topologies for a run time re-routable network on a programmable chipDavid A. Kearney, Gerard Veldman. 178-185 [doi]
- A high-speed ray tracing engine built on a field-programmable systemJoshua Fender, Jonathan Rose. 188-195 [doi]
- Reconfigurable real-time address trace compressor for embedded microprocessorsShyh-Ming Huang, Ing-Jer Huang, Chung-Fu Kao. 196-203 [doi]
- Customising parallelism and caching for machine learningAndreas Fidjeland, Wayne Luk. 204-211 [doi]
- A low cost FPGA system for high speed face detection and trackingStavros Paschalakis, Miroslaw Bober. 214-221 [doi]
- An autonomous flying object navigated by real-time optical flow and visual target detectionHitoshi Yamada, Takashi Tominaga, Michinori Ichikawa. 222-227 [doi]
- FPGA based EBCOT architecture for JPEG 2000Manjunath Gangadhar, Dinesh Bhatia. 228-233 [doi]
- FPGA-based computation of free-form deformations in medical image registrationJun Jiang, Wayne Luk, Daniel Rueckert. 234-241 [doi]
- DIMES: an iterative emulation platform for Multiprocessor-System-On-Chip designsHirofumi Sakane, Levent Yakay, Vishal Karna, Clement Leung, Guang R. Gao. 244-251 [doi]
- TKDM - a reconfigurable co-processor in a PC's memory slotChristian Plessl, Marco Platzner. 252-259 [doi]
- Performance-driven recursive multi-level clusteringMehrdad Eslami Dehkordi, Stephen Dean Brown. 262-269 [doi]
- Design space exploration with A Stream CompilerOskar Mencer, David J. Pearce, Lee W. Howes, Wayne Luk. 270-277 [doi]
- Source-directed transformations for hardware compilationJosé Gabriel F. Coutinho, Wayne Luk. 278-285 [doi]
- An FPGA based coprocessor for 3D affine transformationsFaycal Bensaali, Abbes Amira, Ahmed Bouridane. 288-291 [doi]
- An FPGA based coprocessor for large matrix product implementationFaycal Bensaali, Abbes Amira, Ahmed Bouridane. 292-295 [doi]
- Using FPGA to implement a n-channel arbitrary waveform generator with various add-on functionsJen-Wei Hsieh, Guo-Ruey Tsai, Min-Chuan Lin. 296-298 [doi]
- Design of FPGA-based adaptive remote calibration control systemYuan-Long Jeang, Liang-Bi Chen, Chia-Pin Huang, Yu-Hsiang Hsu, Ming-Yu Yeh, Kai-Ming Yang. 299-302 [doi]
- Performance optimization of an FPGA-based configurable multiprocessor for matrix operationsXiaofang Wang, Sotirios G. Ziavras. 303-306 [doi]
- Bayesian digital terrain model reconstruction on Virtex-II FPGAHan Tao, Toh Lik Khoong, Chai Geok Ling Serena. 307-310 [doi]
- A coarse-grained reconfigurable architecture with low cost configuration data compression mechanismKazuya Tanigawa, Takashi Kawasaki, Tetsuo Hironaka. 311-314 [doi]
- An embedded in-circuit emulator generator for SOC platformYuan-Long Jeang, Liang-Bi Chen, Yi-Ting Chou, Hsin-Chia Su. 315-318 [doi]
- A crystal-based digital ring oscillatorSeyed Reza Abdollahi, Seyed Mehdi Fakhraei, Bertan Bakkaloglu, Mahmoud Kamarei. 319-322 [doi]
- A parameterized automatic cache generator for FPGAsPeter Yiannacouras, Jonathan Rose. 324-327 [doi]
- A field-customizable and runtime-adaptable microarchitectureToshinori Sato, Daisuke Morishita. 328-331 [doi]
- On-chip communication architectures for reconfigurable System-on-ChipAndy Lee, Neil W. Bergmann. 332-335 [doi]
- Three video applications using an FPGA based pyramid implementation: Tracking, Mosaics and StabilizationMarco Aurelio Nuño-Maganda, Miguel O. Arias-Estrada, Claudia Feregrino Uribe. 336-339 [doi]
- The Egret platform for reconfigurable system on chipNeil W. Bergmann, John Williams. 340-343 [doi]
- A temporal partitioning approach based on reconfiguration granularity estimation for dynamically reconfigurable systemsXue-Jie Zhang, Kam-Wing Ng. 344-347 [doi]
- Beyond performance: secure and fair memory management for multiple systems on a chipCarlos Macián, Sarang Dharmapurikar, John W. Lockwood. 348-351 [doi]
- Double precision floating-point arithmetic on FPGAsStavros Paschalakis, Peter Lee 0002. 352-358 [doi]
- Temporal task clustering for online placement on reconfigurable hardwareAli Ahmadinia, Christophe Bobda, Jürgen Teich. 359-362 [doi]
- Reconfigurable parallel comparation architecture and its application to IP packet filtersNoriyuki Aibe, Moritoshi Yasunaga. 363-366 [doi]
- Reconfigurable architecture for probabilistic neural network systemRyosuke Mizuno, Noriyuki Aibe, Moritoshi Yasunaga, Ikuo Yoshihara. 367-370 [doi]
- Parallel image processing field programmable gate array for real time image processing systemTakeaki Sugimura, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi. 372-374 [doi]
- Artificial neural networks as building blocks of mixed signal FPGAR. Manjunath, K. S. Gurumurthy. 375-378 [doi]
- Specification and integration of software and reconfigurable hardware using Hardware Join JavaJohn Hopf, David A. Kearney. 379-382 [doi]
- Architecture template with dynamic buffering for runtime reconfiguration of adaptive embedded communication systemsDirk Eilers, Helmut Steckenbiller, Rudi Knorr. 383-386 [doi]
- Accelerating signal processing algorithms in digital holography using an FPGA platformThomas Lenart, Viktor Öwall, Mats Gustafsson, Mikael Sebesta, Peter Egelberg. 387-390 [doi]
- A new approach for reconfigurable massively parallel computersChristophe Bobda, Klaus Danne, Ali Ahmadinia, Jürgen Teich. 391-394 [doi]
- An FPGA implementation of a special purpose processor for steganographyHala A. Farouk, Magdy Saeb. 395-398 [doi]
- Comparing the bitstreams of applications specified in Hardware Join Java and HandelCJohn Hopf. 399-402 [doi]
- Abstractions and primitives enabling runtime resource allocation for dynamic IP cores using virtual platform FPGAsDavid A. Kearney, Gerard Veldman, David Warren. 403-406 [doi]
- Combined run-time area allocation and long line re-routing for reconfigurable computingMark Jasiunas. 407-410 [doi]
- A concurrent multi-bank memory arbiter for dynamic IP cores using idle skip round robinDavid A. Kearney, Gerard Veldman. 411-414 [doi]
- Augmenting general purpose processors for network processingHamid Reza Ghasemi, Hossein Mohammadi, Behnam Robatmili, Nasser Yazdani. 416-419 [doi]
- Design of low cost FPGA based PCI Bus SnifferChee Wei Liang, Noohul Basheer Zain Ali, Ramesh Seth Nair. 420-423 [doi]
- FPGA implementation of real-time image convolutions with three level of memory hierarchyHongtu Jiang, Viktor Öwall. 424-427 [doi]
- Fault injection into SRAM-based FPGAs for the analysis of SEU effectsGhazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Alireza Ejlali. 428-430 [doi]
- Compiling to FPGAs via an EPIC compiler's intermediate representationZhiguo Ge, Jirong Liao, Weng-Fai Wong. 431-434 [doi]
- Mapping computation kernels to clustered programmable-reconfigurable processorsJeffrey J. Cook, Lee Baugh, Derek B. Gottlieb, Nicholas P. Carter. 435-438 [doi]
- Multisensor inversion with high-performance FPGA computationYongxiang Hu, Yang Cai, Mark Tomzak, Tsengdar Lee. 439-442 [doi]
- Exploiting system-level parallelism in the application development on a reconfigurable computerEsam El-Araby, Mohamed Taher, Kris Gaj, Tarek A. El-Ghazawi, David Caliga, Nikitas A. Alexandridis. 443-446 [doi]
- The Multiplier Tree FIR filter architectureAlex Carreira, Trevor W. Fox. 447-450 [doi]
- FPGA implementable architecture for geometric global positioningAnant Utgikar, Guna Seetharaman, Ha Vu Le. 451-455 [doi]