Table of Contents

• Invited Keynote 1: Closing the gap between FPGAs and ASICsJonathan Rose. [doi]
• Invited Keynote 2: Applications of programmable logic in modern particle physics experimentsGeoff Hall. [doi]
• Enhancing the area-efficiency of FPGAs with hard circuits using shadow clustersPeter Jamieson, Jonathan Rose. 1-8 [doi]
• Granularity aspects for the design of multi-level reconfigurable architecturesSebastian Lange, Martin Middendorf. 9-16 [doi]
• Evaluation of granularity on threshold voltage control in flex power FPGAMasakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike. 17-24 [doi]
• Robust and real-time automatic target recognition using partial hausdorff distance measure on reconfigurable hardwareJinbo Xu, Yong Dou. 25-32 [doi]
• Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentationDong-U Lee, Ray C. C. Cheung, John D. Villasenor, Wayne Luk. 33-40 [doi]
• Seed-based genomic sequence comparison using a FPGA/FLASH acceleratorDominique Lavenier, Xinchun Liu, Gilles Georges. 41-48 [doi]
• An FPGA implementation of the simplex algorithmSamuel Bayliss, Christos-Savvas Bouganis, George A. Constantinides, Wayne Luk. 49-56 [doi]
• On-line scheduling of real-time tasks for reconfigurable computing systemXuegong Zhou, Ying Wang, XunZhang Huang, Chenglian Peng. 57-64 [doi]
• Efficient algorithm for functional scheduling in hardware/software co-designWu Jigang, Thambipillai Srikanthan, Tao Jiao. 65-72 [doi]
• Generating hardware from OpenMP programsY. Y. Leow, C. Y. Ng, Weng-Fai Wong. 73-80 [doi]
• Reconfigurable FLUX networksStamatis Vassiliadis, Ioannis Sourdis. 81-88 [doi]
• Interconnect driver design for long wires in field-programmable gate arraysEdmund Lee 0002, Guy Lemieux, Shahriar Mirabbasi. 89-96 [doi]
• Within-die delay variability in 90nm FPGAs and beyondN. Pete Sedcole, Peter Y. K. Cheung. 97-104 [doi]
• A highly parameterizable parallel processor array architectureDmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich. 105-112 [doi]
• Optimizing the critical loop in the H.264/AVC CABAC decoderHendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt, Vincent Nollet. 113-118 [doi]
• Regular expression matching for reconfigurable packet inspectionJoão Bispo, Ioannis Sourdis, João M. P. Cardoso, Stamatis Vassiliadis. 119-126 [doi]
• Automated design space exploration of FPGA-based FFT architectures based on area and power estimationMiguel A. Sánchez Marcos, Mario Garrido, Marisa López-Vallejo, Carlos A. López-Barrio. 127-134 [doi]
• Sigma-delta based clock recovery using on-chip PLL in FPGANing Ge, Yuyu Liu, Huazhong Yang, Hui Wang 0004. 135-140 [doi]
• A hardware cache memcpy acceleratorStephan Wong, Filipa Duarte, Stamatis Vassiliadis. 141-148 [doi]
• A novel memory architecture for elliptic curve cryptography with parallel modular multipliersRalf Laue 0002, Sorin A. Huss. 149-156 [doi]
• Memory support design for LU decomposition on the starbridge hyper-computerSeth Young, Arvind Sudarsanam, Aravind Dasu, Thomas Hauser. 157-164 [doi]
• FPGA-based MSB-first bit-serial variable block size motion estimation processorBrian M. H. Li, Philip Heng Wai Leong. 165-172 [doi]
• FPGA accelerated tate pairing based cryptosystems over binary fieldsChang Shu 0003, Soonhak Kwon, Kris Gaj. 173-180 [doi]
• A comparison of 2-D discrete wavelet transform computation schedules on FPGAsMaria E. Angelopoulou, Konstantinos Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos. 181-188 [doi]
• Perturber: semi-synthetic circuit generation using ancestor control for testing incremental place and routeDavid Grant, Guy Lemieux. 189-196 [doi]
• Multithreaded virtual-memory-enabled reconfigurable hardware acceleratorsMiljan Vuletic, Paolo Ienne, Christopher Claus, Walter Stechele. 197-204 [doi]
• FPGA core watermarking based on power signature analysisDaniel Ziener, Jürgen Teich. 205-212 [doi]
• FPGA acceleration of the tate pairing in characteristic 2Robert Ronan, Colm O'Eigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins. 213-220 [doi]
• FADES: a fault emulation tool for fast dependability assessmentDavid de Andrés, Juan Carlos Ruiz, Daniel Gil, Pedro J. Gil. 221-228 [doi]
• An adaptive frequency control method using thermal feedback for reconfigurable hardware applicationsPhillip H. Jones, Young H. Cho, John W. Lockwood. 229-236 [doi]
• FPGA implementation of a fuzzy controller for automobile DC-DC convertersJacobo Álvarez, Alfonso Lago, Andres Nogueiras, Carlos Martinez-Penalver, Jorge Marcos, Jesus Doval-Gandoy, Óscar Lopez. 237-240 [doi]
• An adaptive and predictive architecture for parameterised PIV algorithmsNathalie Bochard, Alain Aubert, Virginie Fresse. 241-244 [doi]
• A real time programmable encoder for low density parity check code targeting a reconfigurable instruction cell architectureZahid Khan, Tughrul Arslan. 245-248 [doi]
• Summarizing a time-sensitive control-flow checking monitoring for multitask systems-on-chipFabian Vargas, Leonardo Picolli, Antonio A. de Alecrim Jr., Marlon Moraes, Marcio Gama. 249-252 [doi]
• Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAsNathalie Chan King Choy, Steven J. E. Wilton. 253-256 [doi]
• Implementation of a real-time multiple input multiple output channel estimator on the smart antenna software radio test system platform using the Xilinx Virtex 2 Pro Field Programmable Gate ArrayPeter J. Green, Desmond P. Taylor. 257-260 [doi]
• Efficient management of custom instructions for run-time reconfigurable instruction set processorsSiew Kei Lam, Bharathi N. Krishnan, Thambipillai Srikanthan. 261-264 [doi]
• FPGA implementation for an iris biometric processorJudith Liu-Jimenez, Raul Sánchez-Reillo, Almudena Lindoso, Oscar Miguel-Hurtado. 265-268 [doi]
• FPGA implementation of tabu search for the quadratic assignment problemShin'ichi Wakabayashi, Yoshihiro Kimura, Shinobu Nagayama. 269-272 [doi]
• Minimizing peak power for application chains on architectures with partial dynamic reconfigurationSudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil Dutt. 273-276 [doi]
• Hardware join Java: a unified hardware/software language for dynamic partial runtime reconfigurable computing applicationsDavid A. Kearney, John Hopf. 277-280 [doi]
• An FPGA based generic prototyping platform employed in a CMOS laser Doppler blood flow cameraYiqun Zhu, Barrie Hayes-Gill, Steve Morgan, Nguyen C. Hoang. 281-284 [doi]
• An adaptive Viterbi decoder on the dynamically reconfigurable processorShohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, Hideharu Amano. 285-288 [doi]
• PowerBit - power aware arithmetic bit-width optimizationAltaf Abdul Gaffar, Jonathan A. Clarke, George A. Constantinides. 289-292 [doi]
• Combining hardware reconfiguration and adaptive computation for a novel SoC design methodologyVincenzo Rana, Marco D. Santambrogio, Seda Ogrenci Memik, Donatella Sciuto. 293-296 [doi]
• Hardware channel model for ultra wideband systemsWen-Chih Kan, Gerald E. Sobelman. 297-300 [doi]
• A leakage aware design methodology for power-gated programmable architecturesNarayan Subramanian, Rajarshee P. Bharadwaj, Dinesh Bhatia. 301-304 [doi]
• A C compiler for implementing FPGA based bit-serial DSP systemsDan Cyca, Laurence E. Turner. 305-308 [doi]
• Performance evaluations of ReconfigMEGrant B. Wigley, David A. Kearney. 309-312 [doi]
• Power estimation of a LUT-based MPGAFrancisco-Javier Veredas, Hans-Jörg Pfleiderer. 313-316 [doi]
• An FPGA-based floating-point processor array supporting a high-precision dot productFritz Mayer-Lindenberg, Valerij Beller. 317-320 [doi]
• Communications infrastructure generation for modular FPGA reconfigurationShannon Koh, Oliver Diessel. 321-324 [doi]
• Fuzzy modular multiplication architecture and low complexity IPR-protection for FPGA technologyAbdulrahman Hanoun, Wael Adi, Friedrich Mayer-Lindenberg, Bassel Soudan. 325-328 [doi]
• th componentsTakashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike. 329-332 [doi]
• The cost of data dependence in motion vector estimation for reconfigurable platformsSu-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung. 333-336 [doi]
• Comparing floating-point and logarithmic number representations for reconfigurable accelerationHaohuan Fu, Oskar Mencer, Wayne Luk. 337-340 [doi]
• Dynamically reconfigurable protocol transducerShota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita. 341-344 [doi]
• Optimal temporal partitioning based on slowdown and retimingChristian Plessl, Marco Platzner, Lothar Thiele. 345-348 [doi]
• Modeling of glitch effects in FPGA based arithmetic circuitsAltaf Abdul Gaffar, Jonathan A. Clarke, George A. Constantinides. 349-352 [doi]
• Design and validation of execution schemes for dynamically reconfigurable architecturesTobias Oppold, Sven Eisenhardt, Wolfgang Rosenstiel. 353-356 [doi]
• Periodic licensing of FPGA based intellectual propertyNathaniel Couture, Kenneth B. Kent. 357-360 [doi]
• A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/OsMasato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani. 361-364 [doi]
• A statistical framework for dimensionality reduction implementation in FPGAsChristos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung. 365-368 [doi]
• Hardalign: a parallel pairwise alignment hardware applicationGuilherme L. Moritz, Heitor S. Lopes, Carlos R. Erig Lima. 369-372 [doi]
• Decoy circuits for FPGA design protectionBradley D. Christiansen, Yong C. Kim, Robert W. Bennington, Christopher J. Ristich. 373-376 [doi]
• Hardware architectures for Monte-Carlo based financial simulationsDavid B. Thomas, Jacob A. Bower, Wayne Luk. 377-380 [doi]
• Customizable FPGA-based architecture for video applications in real timeGriselda Saldaña, Miguel Arias-Estrada. 381-384 [doi]
• Super fast hardware string matchingChia-Tien Dan Lo, Yi-Gang Tai, Kleanthis Psarris, Wen-Jyi Hwang. 385-388 [doi]