Abstract is missing.
- Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopyJunyi Xie, Xinyu Niu, Andy K. S. Lau, Kevin K. Tsia, Hayden Kwok-Hay So. 1-8 [doi]
- FPGA acceleration of reference-based compression for genomic dataJames Arram, Moritz Pflanzer, Thomas Kaplan, Wayne Luk. 9-16 [doi]
- Leftmost longest regular expression matching in reconfigurable logicKubilay Atasu. 17-23 [doi]
- Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGAAndrew Bitar, Mohamed S. Abdelfattah, Vaughn Betz. 24-31 [doi]
- An adaptive virtual overlay for fast trigger insertion for FPGA debugFatemeh Eslami, Steven J. E. Wilton. 32-39 [doi]
- Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAsJeffrey Goeders, Steven J. E. Wilton. 40-47 [doi]
- Using source-to-source compilation to instrument circuits for debug with High Level SynthesisJoshua S. Monson, Brad L. Hutchings. 48-55 [doi]
- QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlayCheng Liu, Ho-Cheung Ng, Hayden Kwok-Hay So. 56-63 [doi]
- Energy minimization in the time-space continuumHyunseok Park, Shreel Vijayvargiya, André DeHon. 64-71 [doi]
- Automatic FPGA system and interconnect construction with multicast and customizable topologyAlex Rodionov, Jonathan Rose. 72-79 [doi]
- Improved carry chain mapping for the VTR flowAna Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne. 80-87 [doi]
- HETRIS: Adaptive floorplanning for heterogeneous FPGAsKevin E. Murray, Vaughn Betz. 88-95 [doi]
- Analyzing the divide between FPGA academic and commercial resultsElias Vansteenkiste, Alireza Kaviani, Henri Fraisse. 96-103 [doi]
- OpenCL library of stream memory components targeting FPGAsJasmina Vasiljevic, Ralph Wittig, Paul Schumacher, Jeff Fifield, Fernando Martinez-Vallina, Henry Styles, Paul Chow. 104-111 [doi]
- Exploring pipe implementations using an OpenCL framework for FPGAsVincent Mirian, Paul Chow. 112-119 [doi]
- An exact MCMC accelerator under custom precision regimesShuanglong Liu, Grigorios Mingas, Christos-Savvas Bouganis. 120-127 [doi]
- FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDICJianfeng Zhang, Paul Chow, Hengzhu Liu. 128-135 [doi]
- Braiding: A scheme for resolving hazards in kernel adaptive filtersStephen Tridgell, Duncan J. M. Moss, Nicholas J. Fraser, Philip H. W. Leong. 136-143 [doi]
- Custom-sized caches in application-specific memory hierarchiesFelix Winterstein, Kermin Fleming, Hsin-Jung Yang, John Wickerson, George A. Constantinides. 144-151 [doi]
- Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardwareJongsok Choi, Stephen Dean Brown, Jason Helge Anderson. 152-159 [doi]
- Provably Correct Development of reconfigurable hardware designs via equational reasoningIan Graves, Adam M. Procter, William L. Harrison, Gerard Allwein. 160-171 [doi]
- Behavioral-level IP integration in high-level synthesisLiwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow. 172-175 [doi]
- Optimized high-level synthesis of SMT multi-threaded hardware acceleratorsJens Huthmann, Andreas Koch 0001. 176-183 [doi]
- Minimizing DSP block usage through multi-pumpingBajaj Ronak, Suhaib A. Fahmy. 184-187 [doi]
- An adaptive cross-layer fault recovery solution for reconfigurable SoCsJifang Jin, Jian Yan, Xuegong Zhou, Lingli Wang. 188-191 [doi]
- A co-design approach for accelerated SQL query processing via FPGA-based data filteringAndreas Becher, Daniel Ziener, Klaus Meyer-Wegener, Jürgen Teich. 192-195 [doi]
- A self-aware data compression system on FPGA in HadoopYubin Li, Yuliang Sun, Guohao Dai, Yuzhi Wang, Jiacai Ni, Yu Wang, Guoliang Li, Huazhong Yang. 196-199 [doi]
- An FPGA-based real-time simultaneous localization and mapping systemMengyuan Gu, Kaiyuan Guo, Wenqiang Wang, Yu Wang, Huazhong Yang. 200-203 [doi]
- Hardware design of a fast, parallel Random Tree path plannerSize Xiao, Adam Postula, Neil W. Bergmann. 204-207 [doi]
- Lower precision for higher accuracy: Precision and resolution exploration for shallow water equationsJames Stanley Targett, Xinyu Niu, Francis P. Russell, Wayne Luk, Stephen Jeffress, Peter D. Düben. 208-211 [doi]
- Comparison of thread signatures for error detection in hybrid multi-coresSebastian Meisner, Marco Platzner. 212-215 [doi]
- Advanced Bayer demosaicing on FPGAsDonald Bailey, Sharmil Randhawa, Jim S. Jimmy Li. 216-220 [doi]
- JIT trace-based verification for high-level synthesisLiwei Yang, Magzhan Ikram, Swathi Gurumani, Suhaib Fahmy, Deming Chen, Kyle Rupnow. 228-231 [doi]
- Cryptographic techniques in redundant number systemsJason Motha, Andrew Bainbridge-Smith, Steve Weddell. 232-235 [doi]
- 2D Discrete Fourier Transform with simultaneous edge artifact removal for real-time applicationsFaisal Mahmood, Mart Toots, Lars-Goran Ofverstedt, Ulf Skoglund. 236-239 [doi]
- FPGA based acceleration of FDAS module for Pulsar SearchHaomiao Wang, Oliver Sinnen. 240-243 [doi]
- FPGA implementation of a SIMD-based array processor with torus interconnectYuki Murakami. 244-247 [doi]
- An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engineBony H. K. Chen, Paul Y. S. Cheung, Peter Y. K. Cheung, Yu-Kwong Kwok. 248-251 [doi]
- Smart camera for Trax playing robotDonald G. Bailey. 252-255 [doi]
- Development of a Trax Artificial Intelligence algorithm using path and edgeRyo Okuda, Tomohiro Tanaka, Keisuke Yamamoto, Takumu Yahagi, Kazuya Tanigawa. 256-259 [doi]
- FPGA Trax Solver based on a neural network designTakumi Fujimori, Tomoya Akabe, Yoshizumi Ito, Kouta Akagi, Shinya Furukawa, Hiroki Shinba, Aoi Tanibata, Minoru Watanabe. 260-263 [doi]
- An architecture-algorithm co-design of artificial intelligence for Trax playerQing Lu, Chiu-Wing Sham, Francis C. M. Lau. 264-267 [doi]
- An Implementation of Trax player using programmable SoCAkira Kojima. 268-271 [doi]
- Trax solver on Zynq with Deep Q-NetworkNaru Sugimoto, Takuji Mitsuishi, Takahiro Kaneda, Chiharu Tsuruta, Ryotaro Sakai, Hideki Shimura, Hideharu Amano. 272-275 [doi]