Table of Contents

• Autonomous Driving System implemented on Robot Car using SoC FPGAAkira Kojima. 1-4 [doi]
• An autonomous driving system utilizing image processing accelerated by FPGAKazunari Takasaki, Kota Hisafuru, Ryotaro Negishi, Kazuki Yamashita, Keisuke Fukada, Tomoya Wakaizumi, Nozomu Togawa. 1-4 [doi]
• A streaming hardware architecture for real-time SIFT feature extractionHector A. Li Sanchez, Alan D. George. 1-9 [doi]
• StreamZip: Compressed Sliding-Windows for Stream AggregationPrajith Ramakrishnan Geethakumari, Ioannis Sourdis. 1-9 [doi]
• Energy-efficient FPGA-accelerated LiDAR-based SLAM for embedded roboticsMarcel Flottmann, Marc Eisoldt, Julian Gaal, Marc Rothmann, Marco Tassemeier, Thomas Wiemann, Mario Porrmann. 1-6 [doi]
• Profiling-Based Control-Flow Reduction in High-Level SynthesisAustin Liolli, Omar Ragheb, Jason Helge Anderson. 1-6 [doi]
• FastCGRA: A Modeling, Evaluation, and Exploration Platform for Large-Scale Coarse-Grained Reconfigurable ArraysSu Zheng, Kaisen Zhang, Yaoguang Tian, Wenbo Yin, Lingli Wang, Xuegong Zhou. 1-10 [doi]
• APIR-DSP: An approximate PIR-DSP architecture for error-tolerant applicationsYuan Dai, Simin Liu, Yao Lu, Hao Zhou, SeyedRamin Rasoulinezhad, Philip H. W. Leong, Lingli Wang. 1-8 [doi]
• A modular RFSoC-based approach to interface superconducting quantum bitsRichard Gebauer, Nick Karcher, Oliver Sander. 1-9 [doi]
• A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space PartitioningThiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura. 1-10 [doi]
• Exponential sine sweep measurement implementation targeting FPGA platformsAlexander Klemd, Patrick Nowak, Piero Rivera Benois, Etienne Gerat, Udo Zölzer, Bernd Klauer. 1-6 [doi]
• An efficient RTL buffering scheme for an FPGA-accelerated simulation of diffuse radiative transferKazuki Furukawa, Ryohei Kobayashi, Tomoya Yokono, Norihisa Fujita, Yoshiki Yamaguchi, Taisuke Boku, Kohji Yoshikawa, Masayuki Umemura. 1-9 [doi]
• StreamSVD: Low-rank Approximation and Streaming Accelerator Co-designZhewen Yu, Christos-Savvas Bouganis. 1-9 [doi]
• Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGAHan-Sok Suh, Jian Meng, Ty Nguyen, Shreyas K. Venkataramanaiah, Vijay Kumar 0001, Yu Cao 0001, Jae-sun Seo. 1-9 [doi]
• On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop AcceleratorsTiago Santos, Nuno Paulino 0001, João Bispo, João M. P. Cardoso, João Canas Ferreira. 1-4 [doi]
• LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGAJingbo Gao, Yu Qian, Yihan Hu, Xitian Fan, Wai-Shing Luk, Wei Cao 0002, Lingli Wang. 1-9 [doi]
• StateLink: FPGA System Debugging via Flexible Simulation/Hardware IntegrationSameh Attia, Vaughn Betz. 1-10 [doi]
• A Hexagon-Based Honeycomb Routing Architecture for FPGAKaichuang Shi, Hao Zhou, Lingli Wang. 1-6 [doi]
• An area-efficient multiply-accumulation architecture and implementations for time-domain neural processingIchiro Kawashima, Yuichi Katori, Takashi Morie, Hakaru Tamukoh. 1-4 [doi]
• High-Performance Hardware Implementation of CRYSTALS-DilithiumLuke Beckwith, Duc Tri Nguyen, Kris Gaj. 1-10 [doi]
• High-performance pipeline architecture for packet classification accelerator in DPUJing Tan, Gaofeng Lv, Yanni Ma, Guanjie Qiao. 1-4 [doi]
• AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAsNajdet Charaf, Christoph Tietz, Michael Raitza, Akash Kumar 0001, Diana Göhringer. 1-6 [doi]
• General routing architecture modelling and exploration for modern FPGAsJiadong Qian, Yuhang Shen, Kaichuang Shi, Hao Zhou, Lingli Wang. 1-9 [doi]
• Characterization of IOBUF-based Ring OscillatorsJulia Burgiel, Daniel E. Holcomb, Ilias Giechaskiel, Shanquan Tian, Jakub Szefer. 1-4 [doi]
• A dataset generation for object recognition and a tool for generating ROS2 FPGA nodeHayato Amano, Hayato Mori, Akinobu Mizutani, Tomohiro Ono, Yuma Yoshimoto, Takeshi Ohkawa, Hakaru Tamukoh. 1-4 [doi]
• Low Precision Networks for Efficient Inference on FPGAsRuth Abra, Dmitry Denisenko, Richard Allen, Tim Vanderhoek, Sarah Wolstencroft, Peter M. Gibson. 1-5 [doi]
• Efficient Queue-Balancing Switch for FPGAsPhilippos Papaphilippou, Kentaro Sano, Boma A. Adhi, Wayne Luk. 1-5 [doi]
• Tens of gigabytes per second JSON-to-Arrow conversion with FPGA acceleratorsJohan Peltenburg, Ákos Hadnagy, Matthijs Brobbel, Robert Morrow, Zaid Al-Ars. 1-9 [doi]
• Real-time Implementation of Cyclostationary Analysis using FPGAsJingyi Li. 1-4 [doi]
• SoC FPGA implementation of an unmanned mobile vehicle with an image transmission system over VNCKeigo Motoyoshi, Yuta Imamura, Taichi Saikai, Koki Fujita, Daiki Furukawa, Masatomo Matsuda, Tatsuma Mori, Yasutoshi Araki, Takehiro Miura, Keizo Yamashita, Haruto Ikehara, Kaito Ohira, Katsuaki Kamimae, Takuho Kawazu, Masahiro Nishimura, Shintaro Matsui, Koki Tomonaga, Taito Manabe, Yuichiro Shibata. 1-4 [doi]
• Fast controling autonomous vehicle based on real time image processingHossein Borhanifar, Hamed Jani, Mohammad Mahdi Gohari, Amir Hossein Heydarian, Mostafa Lashkari, Mohammad Reza Lashkari. 1-4 [doi]
• Parallel-Pipeline Fast Walsh-Hadamard Transform Implementation Using HLSA. Manjarres Garcia, Carlos Alexander Osorio Quero, Jose de Jesus Rangel-Magdaleno, José Martínez-Carranza, Daniel Durini Romero. 1-4 [doi]
• Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed DatabasesJohannes Wirth, Jaco A. Hofmann, Lasse Thostrup, Carsten Binnig, Andreas Koch 0001. 1-9 [doi]
• High performance lattice regression on FPGAs via a high level hardware description languageNathan Zhang, Matthew Feldman, Kunle Olukotun. 1-10 [doi]
• FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis ExamplePedro Filipe Silva, João Bispo, Nuno Paulino 0001. 1-4 [doi]
• Optimizing Bayesian Recurrent Neural Networks on an FPGA-based AcceleratorMartin Ferianc, Zhiqiang Que, Hongxiang Fan, Wayne Luk, Miguel Rodrigues. 1-10 [doi]
• Resource-saving FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslimYing Jie Yan, Hideharu Amano, Masashi Aono, Kaori Ohkoda, Shingo Fukuda, Kenta Saito, Seiya Kasai. 1-5 [doi]
• 2SLAM: FPGA Accelerated High-Accuracy SLAM with Heapsort and Parallel Keypoint ExtractorCheng Wang, Yingkun Liu, Kedai Zuo, Jianming Tong, Yan Ding, Pengju Ren. 1-9 [doi]
• A unified accelerator design for LiDAR SLAM algorithms for low-end FPGAsKeisuke Sugiura, Hiroki Matsutani. 1-9 [doi]
• Total-ionizing-dose tolerance evaluation of an optoelectronic field programmable gate array VLSI during operationHirotoshi Ito, Minoru Watanabe. 1-4 [doi]
• An FPGA-Based Image Recognition with Remote Update Functions for Autonomous Driving on "ad-refkit"Hyuga Hashimoto, Ryo Naka, Yasutaka Wada. 1-3 [doi]
• Parallelized Technology Mapping to General PLBs by Adaptive Circuit PartitioningXiaoxi Wang, Moucheng Yang, Zhen Li, Lingli Wang. 1-5 [doi]
• Dataflow Systolic Array Implementations of Exploring Dual-Triangular Structure in QR Decomposition Using High-Level SynthesisSiyang Jiang, Hsi-Wen Chen, Ming-Syan Chen. 1-4 [doi]
• Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed NetworksTomás Fukac, Jirí Matousek 0002, Jan Korenek, Lukás Kekely. 1-9 [doi]
• A High-Precision Flexible Symmetry-Aware Architecture for Element-Wise Activation FunctionsXuan Feng, Yue Li, Yu Qian, Jingbo Gao, Wei Cao, Lingli Wang. 1-4 [doi]
• Zytlebot : FPGA integrated ros-based autonomous mobile robotRyota Miyagi, Naofumi Takagi, Sho Kinoshista, Masashi Oda, Hideki Takase. 1-4 [doi]
• In-Storage Computation of Histograms with differential privacyAndrei Tosa, Anca Hangan, Gheorghe Sebestyen, Zsolt István. 1-4 [doi]
• Efficient Physical Page Migrations in Shared Virtual Memory Reconfigurable Computing SystemsTorben Kalkhof, Andreas Koch. 1-10 [doi]
• Efficient Stride 2 Winograd Convolution Method Using Unified Transformation Matrices on FPGAChengcheng Huang, Xiaoxiao Dong, Zhao Li, Tengteng Song, Zhenguo Liu, Lele Dong. 1-9 [doi]
• Development of Autonomous Driving System based on Image Recognition using Programmable SoCsRyohei Yamamoto, Yuki Izumi, Ryo Aono, Takumi Nagahara, Tomonari Tanaka, Wang Liao, Yukio Mitsuyama. 1-4 [doi]
• FLOWER: A comprehensive dataflow compiler for high-level synthesisPuya Amiri, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack. 1-9 [doi]