Table of Contents

• PODS revisited-a study of software failure behaviourPeter G. Bishop, F. D. Pullen. 2-8 [doi]
• A large scale second generation experiment in multi-version software: description and early resultsJohn P. J. Kelly, David E. Jr. Eckhardt, Mladen A. Vouk, David F. McAllister, Alper K. Caglayan. 9-14 [doi]
• In search of effective diversity: a six-language study of fault-tolerant flight control softwareAlgirdas Avizienis, Michael R. Lyu, Werner Schütz. 15-22 [doi]
• A sequential circuit test generation using threshold-value simulationKwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh. 24-29 [doi]
• Advanced automatic test pattern generation and redundancy identification techniquesMichael H. Schulz, Elisabeth Auth. 30-35 [doi]
• Generating pattern sequences for the pseudo-exhaustive test of MOS-circuitsHans-Joachim Wunderlich, Sybille Hellebrand. 36-41 [doi]
• Volatile logging in n-fault-tolerant distributed systemsRobert E. Strom, David F. Bacon, Shaula Yemini. 44-49 [doi]
• Approaches to implementation of a repairable distributed recovery block schemeKwang-Hae Kim, J. C. Yoon. 50-55 [doi]
• Fault tolerant concurrent C: a tool for writing fault tolerant distributed programsRobert F. Cmelik, Narain H. Gehani, William D. Roome. 56-61 [doi]
• Computational complexity of controllability/observability problems for combinational circuitsHideo Fujiwara. 64-69 [doi]
• An iterative technique for calculating aliasing probability of linear feedback signature registersAndré Ivanov, Vinod K. Agarwal. 70-75 [doi]
• RIDDLE: a foundation for test generation on a high level design descriptionGabriel M. Silberman, Ilan Y. Spillinger. 76-81 [doi]
• Analysis of workload influence on dependabilityJohn F. Meyer, Lu Wei. 84-89 [doi]
• Reliability analysis of non repairable systems using stochastic Petri netsKamel Barkaoui, Gerard Florin, Céline Fraize, Bernard Lemaire, Stéphane Natkin. 90-95 [doi]
• An open layered architecture for dependability analysis and its applicationMarco Mulazzani. 96-101 [doi]
• FIAT-fault injection based automated testing environmentZary Segall, Dalibor F. Vrsalovic, Daniel P. Siewiorek, David A. Yaskin, J. Kownacki, James H. Barton, R. Dancey, A. Robinson, T. Lin. 102-107 [doi]
• On simulating faults in parallelVijay S. Iyengar, Donald T. Tang. 110-115 [doi]
• Accelerated fault simulation by propagating disjoint fault-setsShigeharu Teshima, Naoya Chujo, Noriyoshi Sano, Hiroshi Nagase, Mitsuharu Takigawa. 116-121 [doi]
• A reconvergent fanout analysis for efficient exact fault simulation of combinational circuitsFadi Maamari, Janusz Rajski. 122-127 [doi]
• Fault simulation in a multilevel environment: the MOZART approachGianpiero Cabodi, Silvano Gai, Marco Mezzalama, Paolo Luca Montessoro, Fabio Somenzi. 128-133 [doi]
• Modelling the influence of unreliable software in distributed computer systemsBjarne E. Helvik. 136-141 [doi]
• Dependability evaluation of software fault-toleranceJean Arlat, Karama Kanoun, Jean-Claude Laprie. 142-177 [doi]
• Experimental evaluation of software reliability growth modelsKen-ichi Matsumoto, Katsuro Inoue, Tohru Kikuno, Koji Torii. 148-153 [doi]
• A unified built-in-test scheme: UBISTMichael Nicolaidis. 157-163 [doi]
• An implementation and analysis of a concurrent built-in self-test techniqueRajiv Sharma, Kewal K. Saluja. 164-169 [doi]
• An on-line error-detectable array divider with a redundant binary representation and a residue codeNaofumi Takagi, Shuzo Yajima. 174-179 [doi]
• General linear codes for fault-tolerant matrix operations on processor arraysSuku Nair, Jacob A. Abraham. 180-185 [doi]
• Watchdog parity channels for digital filter protectionBernhard G. Zagar, G. Robert Redinbo. 186-191 [doi]
• Robust search methods for B-treesKikuo Fujimura, Pankaj Jalote. 194-199 [doi]
• Saturation: reduced idleness for improved fault-toleranceJean-Claude Fabre, Yves Deswarte, Jean-Claude Laprie, David Powell. 200-205 [doi]
• Agreeing on who is present and who is absent in a synchronous distributed systemFlaviu Cristian. 206-211 [doi]
• An easily testable parallel multiplierSung Je Hong. 214-219 [doi]
• On the design of robust testable CMOS combinational logic circuitsSandip Kundu, Sudhakar M. Reddy. 220-225 [doi]
• The design of fast totally self-checking Berger code checkers based on Berger code partitioningJien-Chung Lo, Suchai Thanawastien. 226-231 [doi]
• The implementation and application of micro rollback in fault-tolerant VLSI systemsYuval Tamir, Marc Tremblay, David A. Rennels. 234-239 [doi]
• Hardware and software fault tolerance: a unified architectural approachJaynarayan H. Lala, Linda S. Alger. 240-245 [doi]
• The Delta-4 approach to dependability in open distributed computing systemsDavid Powell, Gottfried Bonn, Douglas T. Seaton, Paulo Veríssimo, F. Waeselynck. 246-251 [doi]
• Fault tolerant parallel processor architecture overviewRichard E. Harper, Jaynarayan H. Lala, John J. Deyst. 252-257 [doi]
• Almost certain diagnosis for intermittently faulty systemsDouglas M. Blough, Gregory F. Sullivan, Gerald M. Masson. 260-265 [doi]
• On minimizing testing rounds for fault identificationEdward F. Schmeichel, S. Louis Hakimi, M. Otsuka, Geoff Sullivan. 266-271 [doi]
• A recursive procedure for optimally designing a hybrid fault diagnosable systemTohru Kohda, Ken-ichi Abiru. 272-277 [doi]
• A probabilistic method for fault diagnosis of multiprocessor systemsSampath Rangarajan, Donald S. Fussell. 278-283 [doi]
• Diagnostic reasoning in digital systemsKurt H. Thearling, Ravi K. Iyer. 286-291 [doi]
• GEMINI-a logic system for fault diagnosis based on set functionsJanusz Rajski. 292-297 [doi]
• Reliabilities of two fault-tolerant interconnection networksJames T. Blake, Kishor S. Trivedi. 300-305 [doi]
• Fault-tolerant BIBD networksB. E. Aupperle, John F. Meyer. 306-311 [doi]
• Disk dual copy methods and their performanceYitzhak Dishon, T.-S. Liu. 314-319 [doi]
• Reliable design of large crosspoint switching networksAnujan Varma, Joydeep Ghosh, Christos J. Georgiou. 320-325 [doi]
• Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architecturesShantanu Dutt, John P. Hayes. 328-333 [doi]
• A fault-tolerant parallel processor modeled by a linear cellular automatonMasahiro Tsunoyama, Sachio Naito. 334-339 [doi]
• Approaches for the repair of VLSI/WSI RRAMs by row/column deletionFabrizio Lombardi, Wei-Kang Huang. 342-347 [doi]
• Minimum fault coverage in reconfigurable arraysNany Hasan, C. L. Liu. 348-353 [doi]
• Masking asymmetric line faults using semi-distance codesKazumitsu Matsuzawa, Eiji Fujiwara. 354-359 [doi]
• An evaluation of system-level fault tolerance on the Intel hypercube multiprocessorPrithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Jacob A. Abraham. 362-367 [doi]
• An efficient multi-dimensional grids reconfiguration algorithm on hypercubeShyh-Kwei Chen, Chungti Liang, Wei-Tek Tsai. 368-373 [doi]
• The connectivity of hypergraph and the design of fault-tolerant multibus systemsTinghuai Chen, Tai Kang, Rong Yao. 374-379 [doi]
• Multiple stuck-at fault testability of self-testing checkersTakashi Nanya, Samiha Mourad, Edward J. McCluskey. 381-386 [doi]