Abstract is missing.
- Formal Stability Analysis of Control SystemsAsad Ahmed, Osman Hasan, Falah Awwad. 3-17 [doi]
- Modular Verification of Vehicle Platooning with Respect to Decisions, Space and TimeMaryam Kamali, Sven Linker, Michael Fisher 0001. 18-36 [doi]
- Synthesizing and Optimizing FDIR Recovery Strategies from Fault TreesLiana Mikaelyan, Sascha Müller 0005, Andreas Gerndt, Thomas Noll. 37-54 [doi]
- Formal Verification of Random Forests in Safety-Critical ApplicationsJohn Törnblom, Simin Nadjm-Tehrani. 55-71 [doi]
- A Benchmark Library for Parametric Timed Model CheckingÉtienne André. 75-83 [doi]
- Formal Timing Analysis of Digital CircuitsQurat-ul Ain, Osman Hasan. 84-100 [doi]
- Embedding CCSL into Dynamic Logic: A Logical Approach for the Verification of CCSL SpecificationsYuanrui Zhang, Hengyang Wu, Yixiang Chen, Frédéric Mallet. 101-118 [doi]
- Refinement of Statecharts with Run-to-Completion SemanticsKarla Morris, Colin F. Snook, Thai Son Hoang, Robert Armstrong, Michael J. Butler. 121-138 [doi]
- Abstraction Refinement with Path Constraints for 3-Valued Bounded Model CheckingNils Timm, Stefan Gruner. 139-157 [doi]
- Model Transformation with Triple Graph Grammars and Non-terminal SymbolsWilliam da Silva, Max Bureck, Ina Schieferdecker, Christian Hein. 161-177 [doi]