Abstract is missing.
- A porting and optimization of search for neighbour-particle in MPS method for GPU by using OpenACCTakaaki Miyajima, Kenichi Kubota, Naoyuki Fujita. [doi]
- HW/SW Co-design of an IEEE 802.11a/g Receiver on Xilinx Zynq SoC using High-Level SynthesisSajjad Nouri, Jens Rettkowski, Diana Göhringer, Jari Nurmi. [doi]
- High Speed Performance Estimation of Embedded Hard-core Processors in FPGA-based SoCsDeshya Wijesundera, Achintha Ihalage, Alok Prakash, Thambipillai Srikanthan. [doi]
- Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis ToolYuto Ishikawa, Keitaro Yanai, Keisuke Koike, Takefumi Miyoshi, Hironori Nakajo. [doi]
- A Time-Division Multiplexing Ising Machine on FPGAsKasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura. [doi]
- Accelerated Embedded AKAZE Feature Detection Algorithm on FPGALester Kalms, Khaled Mohamed, Diana Göhringer. [doi]
- Dataflow based Near Data Computing Achieves Excellent Energy EfficiencyCharles Shelor, Krishna M. Kavi. [doi]
- FPGA based ASIC Emulator with High Speed Optical Serial LinksMotoki Amagasaki, Futoshi Murase, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi. [doi]
- Reducing the Cost of Removing Border Artefacts in Fourier TransformsDonald G. Bailey, Faisal Mahmood, Ulf Skoglund. [doi]
- HLS Compilation for CPU InterlaysJose Raul Garcia Ordaz, Dirk Koch. [doi]
- Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled AcceleratorsTakahiro Kaneda, Ryotaro Sakai, Naoki Nishikawa, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano. [doi]
- Access Network Generation for Efficient Debugging of FPGAsHabib ul Hasan Khan, Thomas Grimm, Michael Hübner, Diana Göhringer. [doi]
- An Adaptive Demotion Policy for High-Associativity CachesJubee Tada, Masayuki Sato, Ryusuke Egawa. [doi]
- Neural Network Training Acceleration with PSO Algorithm on a GPU Using OpenCLJiajun Li, Qiang Liu. [doi]
- High-Performance Hardware Accelerators for Solving Ordinary Differential EquationsIoannis Stamoulias, Matthias Möller, Rene Miedema, Christos Strydis, Christoforos Kachris, Dimitrios Soudris. [doi]
- Towards Flexible Automatic Generation of Graph Processing GatewareNina Engelhardt, Hayden Kwok-Hay So. [doi]
- FPGA Implementation of A Graph Cut Algorithm For Stereo VisionRyo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri. [doi]
- FPGA-based Stream Computing for High-Performance N-Body Simulation using Floating-Point DSP BlocksKentaro Sano, Shin Abiko, Tomohiro Ueno. [doi]
- Probabilistic Strategies Based on Staged LSH for Speedup of Audio Fingerprint Searching with Ten Million Scale DatabaseMasahiro Fukuda, Yasushi Inoguchi. [doi]
- DTP: Enabling Exhaustive Exploration of FPGA Temporal Partitions for Streaming HPC ApplicationsMostafa Koraei, Magnus Jahre, S. Omid Fatemi. [doi]
- A Case for Remote GPUs over 10GbE Network for VR ApplicationsShin Morishima, Masahiro Okazaki, Hiroki Matsutani. [doi]
- Acceleration of Publish/Subscribe Messaging in ROS-compliant FPGA ComponentYuhei Sugata, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota. [doi]
- FPGA Accelerated NoC-Simulation: A Case Study on the Intel Xeon Phi Ringbus TopologyOliver Jakob Arndt, Christian Spindeldreier, Kevin Wohnrade, Daniel Pfefferkorn, Martin Neuenhahn, Holger Blume. [doi]
- An FPGA NIC Based Hardware Caching for BlockchainYuma Sakakibara, Kohei Nakamura, Hiroki Matsutani. [doi]
- Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCLHiroyuki Noda, Ryotaro Sakai, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano. [doi]
- High-level Synthesis based on Parallel Design Patterns using a Functional LanguageMorihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi. [doi]
- Performance Evaluation of a CPU-FPGA Hybrid Cluster Platform PrototypeYasunori Osana, Yohei Sakamoto. [doi]