Table of Contents

• Embedded Systems as DatacentersBob Iannucci. 1 [doi]
• Larrabee: A Many-Core Intel Architecture for Visual ComputingRoger Espasa. 2 [doi]
• Remote Store ProgrammingHenry Hoffmann, David Wentzlaff, Anant Agarwal. 3-17 [doi]
• Low-Overhead, High-Speed Multi-core Barrier SynchronizationJohn Sartori, Rakesh Kumar. 18-34 [doi]
• Improving Performance by Reducing Aborts in Hardware Transactional MemoryMohammad Ansari, Behram Khan, Mikel Luján, Christos Kotselidis, Chris C. Kirkham, Ian Watson. 35-49 [doi]
• Energy and Throughput Efficient Transactional Memory for Embedded Multicore SystemsCesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy. 50-65 [doi]
• Split Register Allocation: Linear Complexity Without the Performance PenaltyBoubacar Diouf, Albert Cohen, Fabrice Rastello, John Cavazos. 66-80 [doi]
• Trace-Based Data Layout Optimizations for Multi-core ProcessorsOlga Golovanevsky, Alon Dayan, Ayal Zaks, David Edelsohn. 81-95 [doi]
• Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory MultiprocessorsPaul M. Carpenter, Alex Ramírez, Eduard Ayguadé. 96-110 [doi]
• Automatically Tuning Sparse Matrix-Vector Multiplication for GPU ArchitecturesAlexander Monakov, Anton Lokhmotov, Arutyun Avetisyan. 111-125 [doi]
• Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set ExtensionsTheo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne. 126-140 [doi]
• Accelerating XML Query Matching through Custom Stack Generation on FPGAsRoger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras. 141-155 [doi]
• An Application-Aware Load Balancing Strategy for Network ProcessorsRainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf. 156-170 [doi]
• Memory-Aware Application Mapping on Coarse-Grained Reconfigurable ArraysYongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee W. Yoon, Yunheung Paek. 171-185 [doi]
• Maestro: Orchestrating Lifetime Reliability in Chip MultiprocessorsShuguang Feng, Shantanu Gupta, Amin Ansari, Scott A. Mahlke. 186-200 [doi]
• Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip MultiprocessorsYunlian Jiang, Kai Tian, Xipeng Shen. 201-215 [doi]
• RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded ProcessorHouman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil Dutt. 216-231 [doi]
• Performance and Power Aware CMP Thread Allocation ModelingYaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny. 232-246 [doi]
• Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial MatchingMarius Grannæs, Magnus Jahre, Lasse Natvig. 247-261 [doi]
• Scalable Shared-Cache Management by Containing Thrashing WorkloadsYuejian Xie, Gabriel H. Loh. 262-276 [doi]
• SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPsShekhar Srikantaiah, Mahmut T. Kandemir. 277-291 [doi]
• DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory SystemsMagnus Jahre, Marius Grannæs, Lasse Natvig. 292-306 [doi]
• ::::Tagged Procedure Calls:::: (::::TPC::::): Efficient Runtime Support for Task-Based Parallelism on the Cell ProcessorGeorge Tzenakis, Konstantinos Kapelonis, Michail Alvanos, Konstantinos Koukos, Dimitrios S. Nikolopoulos, Angelos Bilas. 307-321 [doi]
• Analysis of Task Offloading for AcceleratorsRoger Ferrer, Vicenç Beltran, Marc González, Xavier Martorell, Eduard Ayguadé. 322-336 [doi]
• Offload - Automating Code Migration to Heterogeneous Multicore SystemsPete Cooper, Uwe Dolinsky, Alastair F. Donaldson, Andrew Richards, Colin Riley, George Russell. 337-352 [doi]
• Computer Generation of Efficient Software Viterbi DecodersFrédéric de Mesmay, Srinivas Chellappa, Franz Franchetti, Markus Püschel. 353-368 [doi]