Abstract is missing.
- Relating buffer-oriented microarchitecture validation to high-level pipeline functionalityNoppanunt Utamaphethai, Ronald D. Blanton, John Paul Shen. 3-8 [doi]
- Automatic validation of pipeline specificationsPrabhat Mishra, Nikil Dutt, Alex Nicolau. 9-13 [doi]
- Automatic test generation for micro-architectural verification of configurable microprocessor cores with user extensionsN. Bhattacharyya, A. Wang. 14-15 [doi]
- Integrating Perl, Tcl and C++ into simulation-based ASIC verification environmentsMichael D. McKinney. 19-24 [doi]
- Symbolic simulation heuristics for high-level design descriptions with uninterpreted functionsKiyoharu Hamaguchi. 25-30 [doi]
- Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional descriptionIrith Pomeranz, Sudhakar M. Reddy. 31-35 [doi]
- Practical use of sequential ATPG for model checking: going the extra mile does pay offMichael S. Hsiao, Jawahar Jain. 39-44 [doi]
- Symbolic simulation techniques-state-of-the-art and applicationsClaudia Blank, Hans Eveking, Jens Levihn, Gerd Ritter. 45-50 [doi]
- A model checking approach to evaluating system level dynamic power management policies for embedded systemsSandeep K. Shukla, Rajesh K. Gupta. 53-57 [doi]
- RTL functional verification using excitation and observation coverageByeong Min, Gwan Choi. 58-63 [doi]
- Improving test quality through resource reallocationAllon Adir, Eitan Marcus, Michal Rimon, Amir Voskoboynik. 64-69 [doi]
- Taylor expansion diagrams: a new representation for RTL verificationMaciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre. 70-75 [doi]
- Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communicationSungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed Amine Jerraya. 79-82 [doi]
- Test pattern generation for timing-induced functional errors in hardware-software systemsSrikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris. 83-88 [doi]
- Combining complex event models and timing constraintsMarek Jersak, Kai Richter, Rolf Ernst. 89-94 [doi]
- Using live sequence charts for hardware protocol specification and compliance verificationAnnette Bunker, Ganesh Gopalakrishnan. 95-100 [doi]
- Proving sequential consistency by model checkingTim Braun, Anne Condon, Alan J. Hu, Kai S. Juse, Marius Laza, Michael Leslie, Rita Sharma. 103-108 [doi]
- TM microprocessor coreShuvendu K. Lahiri, Carl Pixley, Ken Albin. 109-114 [doi]
- (R) 4 multiplierRoope Kaivola, Naren Narasimhan. 115-120 [doi]
- Reducing bitvector satisfiability problems to scale down design sizes for RTL property checkingPeer Johannsen. 123-128 [doi]
- Constraints specification at higher levels of abstractionFelice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli. 129-133 [doi]
- TM custom memories using compositions of abstract specificationsJayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir. 134-141 [doi]
- On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault modelChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. 145-150 [doi]
- Hardware-software covalidation: fault models and test generationIan G. Harris. 151-156 [doi]
- Observability enhanced coverage analysis of C programs for functional validationFarzan Fallah, Indradeep Ghosh. 157-162 [doi]
- Using cutwidth to improve symbolic simulation and Boolean satisfiabilityDong Wang, Edmund M. Clarke, Yunshan Zhu, James H. Kukula. 165-170 [doi]
- An enhanced cut-points algorithm in formal equivalence verificationZurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna. 171-176 [doi]
- An analysis of ATPG and SAT algorithms for formal verificationGanapathy Parthasarathy, Chung-Yang Huang, Kwang-Ting Cheng. 177-182 [doi]