Table of Contents

• Facebook: Server board designHarry Li. 1-20 [doi]
• ARM processor evolution: Bringing high performance to mobile devicesSimon Segars. 1-37 [doi]
• The Maven vector-thread architectureYunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic. 1 [doi]
• Hybrid memory cube (HMC)J. Thomas Pawlowski. 1-24 [doi]
• Integrated inductors with magnetic materials for on-chip power conversionDonald S. Gardner, Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Shekhar Borkar. 1-36 [doi]
• Facebook: Efficient power distribution: 277Vac distribution w/o centralized UPS 95% high efficiency solution battery cabinet as distributed backup energy unitPierluigi Sarti. 1-33 [doi]
• TILE-Gx100 ManyCore processor: Acceleration interfaces and architectureCarl Ramey. 1-21 [doi]
• Sereno: A second generation virtualized network interface controllerMike Galles, Shrijeet Mukherjee. 1-19 [doi]
• Facebook: The open compute projectAmir Michael. 1-41 [doi]
• Practical power gating and dynamic voltage/frequency scalingStephen Kosonocky. 1-62 [doi]
• VENICE: A compact vector processor for FPGA applicationsAaron Severance, Guy Lemieux. 1-5 [doi]
• Rethinking algorithms for future architectures: Communication-avoiding algorithmsJim Demmel. 1-63 [doi]
• The Cavium 32 Core OCTEON II 68xxRichard E. Kessler. 1-33 [doi]
• Tessellation operating system: Building a real-time, responsive, high-throughput client OS for many-core architecturesJuan A. Colmenares, Sarah Bird, Gage Eads, Steven A. Hofmeyr, Albert Kim, Rohit Poddar, Hilfi Alkaff, Krste Asanovic, John Kubiatowicz. 1 [doi]
• Poulson: An 8 core 32 nm next generation Intel® Itanium® processorSteven R. Undy. 1-22 [doi]
• The Blue Gene/Q Compute chipRuud A. Haring. 1-20 [doi]
• Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy BridgeEfi Rotem, Alon Naveh, Doron Rajwan, Avinash Ananthakrishnan, Eliezer Weissmann. 1-33 [doi]
• One billion packet per second frame processing pipelineMike Davies. 1-24 [doi]
• T4: A highly threaded server-on-a-chip with native support for heterogeneous computingRobert T. Golla, Paul J. Jordan. 1-21 [doi]
• 1TOPS/W software programmable media processorDavid Moloney. 1-24 [doi]
• The Intel® Quick Sync Video technology in the 2nd-generation Intel Core processor familyHong Jiang. 1-23 [doi]
• The world's fastest DSP core: Breaking the 100 GMAC/s barrierChris Rowen, Dan Nicolaescu, Rajiv Ravindran, David Heine, Grant Martin, James Kim, Dror E. Maydan, Nupur Andrews, Bill Huffman, Vakis Papaparaskeva, Shay Gal-On, Peter R. Nuth, Pushkar Patwardhan, Manish Paradkar. 1-25 [doi]
• AMD'S "LLANO" Fusion APUDenis Foley, Maurice Steinman, Alexander Branover, Greg Smaus, Antonio Asaro, Swamy Punyamurtula, Ljubisa Bajic. 1-38 [doi]
• XMOS architecture XS1 chipsDavid May 0006. 1-30 [doi]
• High-efficient architecture of Godson-T many-core processorDongrui Fan, Hao Zhang 0009, Da Wang, Xiaochun Ye, Fenglong Song, Junchao Zhang, Lingjun Fan. 1-31 [doi]
• Intel's digital random number generator (DRNG)George Cox, Charles Dike, D. J. Johnston. 1-13 [doi]
• The utility of fast active messages on many-core chips: Efficient supercomputing projectR. Curtis Harting, Vishal Parikh, William J. Dally. 1 [doi]
• A few ways can take you a long way: Efficient and highly associative caches with scalable partitioning for many-core CMPsDaniel Sánchez 0003, Christos Kozyrakis. 1 [doi]
• Efficient fetch mechanism by employing instruction registerMochamad Asri. 1-5 [doi]
• Building a 40 Gbps next generation virtualized security processor: HOT CHIPS 23 - August 2011Jeff Pangborn. 1-21 [doi]
• Challenges of building personal robotsSteve Cousins. 1-36 [doi]
• Bandwidth engine® serial memory chip breaks 2 billion accesses/secMichael J. Miller. 1-23 [doi]
• Fully integrated switched-capacitor DC-DC conversionElad Alon, Hanh-Phuc Le, Seth Sanders. 1-30 [doi]
• High-performance power-efficient x86-64 server and desktop processors using the core codenamed "Bulldozer"Sean White. 1-32 [doi]
• Low-power high-density 10GBASE-T ethernet transceiverRamin Shirani, Ramin Farjadrad. 1-20 [doi]
• SeaMicro SM10000-64 server: Building datacenter servers using cell phone chipsAshutosh Dhodapkar, Gary Lauterbach, Sean Lie, Dhiraj Mallick, Jim Bauman, Sundar Kanthadai, Toru Kuzuhara, Gene Shen, Min Xu, Chris Zhang. 1-18 [doi]
• Xilinx Zynq-7000 EPP: An extensible processing platform familyVidya Rajagopalan, Vamsi Boppana, Sandeep Dutta, Brad Taylor, Ralph Wittig. 1-24 [doi]
• 2nd Generation Intel® Core Processor Family: Intel® Core i7, i5 and i3Oded Lempel. 1-48 [doi]
• Electrons, photons, phonons, wave, bits, and industrial design: Microsoft kinect sensor: Hot chips 23Dawson Yee, Scott McEldowney. 1-20 [doi]