Abstract is missing.
- Configuring multiple scan chains for minimum test timeSridhar Narayanan, Rajesh Gupta, Melvin A. Breuer. 4-8 [doi]
- Overall consideration of scan design and test generationPao-Chuan Chen, Bin-Da Liu, Jhing-Fa Wang. 9-12 [doi]
- Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devicesY. H. Choi, T. Jung. 13-16 [doi]
- An algorithm to reduce test application time in full scan designsSoo-Young Lee, Kewal K. Saluja. 17-20 [doi]
- New channel segmentation model and associated routing algorithm for high performance FPGAsSurendra Burman, Chandar Kamalanathan, Naveed A. Sherwani. 22-25 [doi]
- On channel segmentation design for row-based FPGAsKai Zhu, D. F. Wong. 26-29 [doi]
- Aesthetic routing for transistor schematicsTsung D. Lee, Lawrence P. McNamee. 35-38 [doi]
- A tutorial on logic synthesis for lookup-table based FPGAsRobert J. Francis. 40-47 [doi]
- An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designsJason Cong, Yuzheng Ding. 48-53 [doi]
- Rectification method for lookup-table type FPGA sYuji Kukimoto, Masahiro Fujita. 54-61 [doi]
- AWE macromodels of VLSI interconnect for circuit simulationSeok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage. 64-70 [doi]
- Extension of the asymptotic waveform evaluation technique with the method of characteristicsJ. Eric Bracken, Vivek Raghavan, Ronald A. Rohrer. 71-75 [doi]
- Timing distribution in VHDL behavioral modelsAshish S. Gadagkar, James R. Armstrong. 82-89 [doi]
- McPOWER: a Monte Carlo approach to power estimationRichard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick. 90-97 [doi]
- Exhaustive simulation need not require an exponential number of testsDaniel Brand. 98-101 [doi]
- A unified signal transition graph model for asynchronous control circuit synthesisAlexandre Yakovlev, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli. 104-111 [doi]
- A generalized state assignment theory for transformation on signal transition graphsPeter Vanbekbergen, Bill Lin, Gert Goossens, Hugo De Man. 112-117 [doi]
- On the verification of state-coding in STGsKuan Jen Lin, Chen-Shang Lin. 118-122 [doi]
- Verifying clock schedulesThomas G. Szymanski, Narendra V. Shenoy. 124-131 [doi]
- Graph algorithms for clock schedule optimizationNarendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 132-136 [doi]
- Identification of critical paths in circuits with level-sensitive latchesTimothy M. Burks, Karem A. Sakallah, Trevor N. Mudge. 137-141 [doi]
- Using constraint geometry to determine maximum rate pipeline clockingChuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah. 142-148 [doi]
- HIMALAYAS - a hierarchical compaction system with a minimized constraint setJin-fuw Lee, Donald T. Tang. 150-157 [doi]
- Cloning techniques for hierarchical compactionRavi Varadarajan, Cyrus Bamji. 158-161 [doi]
- An optimal chip compaction method based on shortest path algorithm with automatic jog insertionToru Awashima, Wataru Yamamoto, Masao Sato, Tatsuo Ohtsuki. 162-165 [doi]
- MOSAIC: a tile-based datapath layout generatorGoro Suzuki, Tetsuya Yamamoto, Kyoji Yuyama, Kotaro Hirasawa. 166-170 [doi]
- Automatic compositional minimization in CTL model checkingMassimiliano Chiodo, Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton. 172-178 [doi]
- Verification of systems containing countersEnrico Macii, Bernard Plessier, Fabio Somenzi. 179-182 [doi]
- Automatic generation and verification of sufficient correctness properties for synchronous processorsFilip Van Aelten, Stan Y. Liao, Jonathan Allen, Srinivas Devadas. 183-187 [doi]
- Verification of asynchronous interface circuits with bounded wire delaysSrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang. 188-195 [doi]
- Delay and bus current evaluation in CMOS logic circuitsAbdolreza Nabavi-Lishi, Nicholas C. Rumin. 198-203 [doi]
- Power estimation tool for sub-micron CMOS VLSI circuitsF. Rouatbi, Baher Haroun, Asim J. Al-Khalili. 204-209 [doi]
- A probabilistic timing approach to hot-carrier effect estimationPing-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj. 210-213 [doi]
- CRIS: a test cultivation program for sequential VLSI circuitsDaniel G. Saab, Youssef Saab, Jacob A. Abraham. 216-219 [doi]
- Portable parallel test generation for sequential circuitsBalkrishna Ramkumar, Prithviraj Banerjee. 220-223 [doi]
- Automatic test generation for linear digital systems with bi-level search using matrix transform methodsRabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d Abreu. 224-228 [doi]
- An effective methodology for functional pipeliningTsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin. 230-233 [doi]
- A scheduling method by stepwise expansion in high-level synthesisHironori Komi, Shoichiro Yamada, Kunio Fukunaga. 234-237 [doi]
- Analytic macromodeling and simulation fo tightly-coupled mixed analog-digital circuitsYu-Hsu Chang, Andrew T. Yang. 244-247 [doi]
- Automatic differentiation in circuit simulation and device modelingPeter Feldmann, Robert C. Melville, Shahriar Moinian. 248-253 [doi]
- A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modelingKimon W. Michaels, Andrzej J. Strojwas. 254-257 [doi]
- ETA: electrical-level timing analysisRonn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage. 258-262 [doi]
- An optimal probe testing algorthm for the connectivity verification of MCM substratesSo-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu. 264-267 [doi]
- E-PROOFS: a CMOS bridging fault simulatorGary S. Greenstein, Janak H. Patel. 268-271 [doi]
- On the generation of small dictionaries for fault locationIrith Pomeranz, Sudhakar M. Reddy. 272-279 [doi]
- Efficient partitioning and analysis of digital CMOS-circuitsUwe Hübner, Heinrich Theodor Vierhaus. 280-283 [doi]
- Efficiency improvements for force-directed schedulingWim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jan H. M. Korst, Albert van der Werf, Jef L. van Meerbergen. 286-291 [doi]
- Area optimization of multi-functional processing unitsAlbert van der Werf, M. J. H. Peek, Emile H. L. Aarts, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh. 292-299 [doi]
- HYPER-LP: a system for power minimization using architectural transformationsAnantha Chandrakasan, Miodrag Potkonjak, Jan M. Rabaey, Robert W. Brodersen. 300-303 [doi]
- Maximally fast and arbitrarily fast implementation of linear computationsMiodrag Potkonjak, Jan M. Rabaey. 304-308 [doi]
- Lazy-expansion symbolic expression approximation in SYNAPSteven J. Seda, Marc G. R. Degrauwe, Wolfgang Fichtner. 310-317 [doi]
- Accuate simplification of large symbolic formulaeFrancisco V. Fernández, Ángel Rodríguez-Vázquez, J. D. Martín, José L. Huertas. 318-321 [doi]
- Behavioral simulation for noise in mixed-mode sampled-data systemsEdward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli. 322-326 [doi]
- An efficient multi-view design model for real-time interactive synthesisAllen C.-H. Wu, Tedd Hadley, Daniel Gajski. 328-331 [doi]
- Equivalent design representations and transformations for interactive schedulingRoger P. Ang, Nikil D. Dutt. 332-335 [doi]
- FICOM: a framework for incremental consistency maintenance in multi-representation, structural VLSI databasesRobert C. Armstrong, Jonathan Allen. 336-343 [doi]
- False loops through resource sharingLeon Stok. 345-348 [doi]
- Timing analysis in high-level synthesisAndreas Kuehlmann, Reinaldo A. Bergamaschi. 349-354 [doi]
- Accurate layout area and delay modeling for system level designChampaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul. 355-361 [doi]
- Ravel: assigned-delay compiled-code logic simulationEmily J. Shriver, Karem A. Sakallah. 364-368 [doi]
- Parallel logic and fault simulation algorithms for shared memory vector machinesAbdulla Bataineh, Füsun Özgüner, Imre Szauter. 369-372 [doi]
- Reconfigurable machine and its application to logic diagnosisNaoaki Suganuma, Yukihiro Murata, Satoru Nakata, Shinichi Nagata, Masahiro Tomita, Kotaro Hirano. 373-376 [doi]
- A logic simulation engine based on a modified data flow architectureAusif Mahmood, William I. Baker, Jayantha A. Herath, Anura P. Jayasumana. 377-380 [doi]
- Maze router without a grid mapJiri Soukup. 382-385 [doi]
- Detailed layer assignment for MCM routingMysore Sriram, Sung-Mo Kang. 386-389 [doi]
- A wire-length minimization algorithm for single-layer layoutsDe-Sheng Chen, Majid Sarrafzadeh. 390-393 [doi]
- System-level routing of mixed-signal ASICs in WRENSujoy Mitra, Sudip Nag, Rob A. Rutenbar, L. Richard Carley. 394-399 [doi]
- On average power dissipation and random pattern testability of CMOS combinational logic networksAmelia Shen, Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer. 402-407 [doi]
- Efficient Boolean function matchingJerry R. Burch, David E. Long. 408-411 [doi]
- ProperSYN: a portable parallel algorithm for logic synthesisKaushik De, Balkrishna Ramkumar, Prithviraj Banerjee. 412-416 [doi]
- A new algorithm for the binate covering problem and its application to the minimization of Boolean relationsSeh-Woong Jeong, Fabio Somenzi. 417-420 [doi]
- A new approach to effective circuit clusteringLars W. Hagen, Andrew B. Kahng. 422-427 [doi]
- A probabilistic multicommodity-flow solution to circuit clustering problemsChing-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin. 428-431 [doi]
- Efficient techniques for inductance extraction of complex 3-D geometriesMattan Kamon, Michael J. Tsuk, C. Smithhisler, Jacob White. 438-442 [doi]
- An analytical method for finding the maximum crosstalk in lossless-coupled transmission linesAli El-Zein, Salim Chowdhury. 443-448 [doi]
- Time domain analysis of nonuniform frequency dependent high-speed interconnectsSanjay L. Manney, Michel S. Nakhla, Qi-Jun Zhang. 449-453 [doi]
- Engineering education: trends and needs (panel)Stephen W. Director, Jonathan Allen, J. Duley. 456 [doi]
- A zero-skew clock routing scheme for VLSI circuitsYing-Meng Li, Marwan A. Jabri. 458-463 [doi]
- Zero skew clock routing in multiple-clock synchronous systemsWasim Khan, Moazzem Hossain, Naveed A. Sherwani. 464-467 [doi]
- HERO: hierarchical EMC-constrained routingDirk Theune, Ralf Thiele, Thomas Lengauer, Anja Feldmann. 468-472 [doi]
- Perfect-balance planar clock routing with minimal path-lengthQing Zhu, Wayne Wei-Ming Dai. 473-476 [doi]
- Design of system interface modulesJane S. Sun, Robert W. Brodersen. 478-481 [doi]
- A partitioning algorithm for system-level synthesisG. Menez, Michel Auguin, Fernand Boéri, C. Carrière. 482-487 [doi]
- Synthesis fo the hardware/software interface in microcontroller-based systemsPai H. Chou, Ross B. Ortega, Gaetano Borriello. 488-495 [doi]
- Assignment of global memory elements for multi-process VHDL specificationsH. Krämer, J. Müller. 496-501 [doi]
- Performance optimization of sequential circuits by eliminating retiming bottlenecksSujit Dey, Miodrag Potkonjak, Steven G. Rothweiler. 504-509 [doi]
- Exploiting multi-cycle false paths in the performance optimization of sequential circuitsPranav Ashar, Sujit Dey, Sharad Malik. 510-517 [doi]
- Valid clocking in wavepipelined circuitsWilliam K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 518-525 [doi]
- Precise timing verification of logic circuits under combined delay modelShinji Kimura, Shigemi Kashima, Hiromasa Haneda. 526-529 [doi]
- DECOR - tightly integrated Design Control and ObservationElisabeth Kupitz, Jürgen Tacken. 532-537 [doi]
- Incorporating design flow management in a framework based CAD systemPeter Bingley, K. Olav ten Bosch, Pieter van der Wolf. 538-545 [doi]
- DAMOCLES: an observer-based approach to design trackingVenu Vasudevan, Yves Mathys, Jim Tolar. 546-551 [doi]
- Test generation for delay faults in non-scan and partial scan sequential circuitsKwang-Ting Cheng. 554-559 [doi]
- An efficient non-enumerative method to estimate path delay fault coverageIrith Pomeranz, Sudhakar M. Reddy. 560-567 [doi]
- COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuitsLakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy. 568-574 [doi]
- Automatic synthesis of 3D asynchronous state machinesKenneth Y. Yun, David L. Dill. 576-580 [doi]
- Automatic gate-level synthesis of speed-independent circuitsPeter A. Beerel, Teresa H. Y. Meng. 581-586 [doi]
- SHILPA: a high-level synthesis system for self-timed circuitsVenkatesh Akella, Ganesh Gopalakrishnan. 587-591 [doi]
- Accurate net models for placement improvement by network flow methodsKonrad Doll, Frank M. Johannes, Georg Sigl. 594-597 [doi]
- Three-phase chip planning - an improved top-down chip planning strategyBernd Schürmann, Joachim Altmeyer, Gerhard Zimmermann. 598-605 [doi]
- Area minimization for general floorplansPeichen Pan, C. L. Liu. 606-609 [doi]
- Behavioral synthesis for testabilityChung-Hsing Chen, Daniel G. Saab. 612-615 [doi]
- Behavioral synthesis for easy testability in data path schedulingTien-Chien Lee, Wayne Wolf, Niraj K. Jha. 616-619 [doi]
- A comparative study of design for testability methods using high-level and gate-level descriptionsVivek Chickermane, Jaushin Lee, Janak H. Patel. 620-624 [doi]
- Exact two-level minimization of hazard-free logic with multiple-input changesSteven M. Nowick, David L. Dill. 626-630 [doi]
- Hazard-non-increasing gate-level optimization algorithmsDavid S. Kung. 631-634 [doi]