Abstract is missing.
- Efficient validity checking for processor verificationRobert B. Jones, David L. Dill, Jerry R. Burch. 2-6 [doi]
- The formal verification of a pipelined double-precision IEEE floating-point multiplierMark Aagaard, Carl-Johan H. Seger. 7-10 [doi]
- Extracting RTL models from transistor netlistsK. J. Singh, P. A. Subrahmanyam. 11-17 [doi]
- Switching activity analysis using Boolean approximation methodTaku Uchino, Fumihiro Minami, Takashi Mitsuhashi, Nobuyuki Goto. 20-25 [doi]
- Estimation and bounding of energy consumption in burst-mode control circuitsPeter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh. 26-33 [doi]
- Statistical estimation of sequential circuit activityTan-Li Chou, Kaushik Roy. 34-37 [doi]
- Efficient reduced-order modeling for the transient simulation of three-dimensional interconnectMike Chou, Jacob K. White. 40-44 [doi]
- Generating sparse partial inductance matrices with guaranteed stabilityByron Krauter, Lawrence T. Pileggi. 45-52 [doi]
- Addressing high frequency effects in VLSI interconnects with full wave model and CFHRamachandra Achar, Michel S. Nakhla, Qi-Jun Zhang. 53-56 [doi]
- Clock distribution design and verification for PowerPC microprocessorsShantanu Ganguly, Shervin Hojat. 58-61 [doi]
- Activity-driven clock design for low power circuitsGustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh. 62-65 [doi]
- Bounded-skew clock and Steiner routing under Elmore delayJason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao. 66-71 [doi]
- Who are the variables in your neighborhoodShipra Panda, Fabio Somenzi. 74-77 [doi]
- Efficient construction of binary moment diagrams for verifying arithmetic circuitsKiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima. 78-82 [doi]
- Be careful with don t caresDaniel Brand, Reinaldo A. Bergamaschi, Leon Stok. 83-86 [doi]
- Pattern generation for a deterministic BIST schemeSybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich. 88-94 [doi]
- Test register insertion with minimum hardware costAlbrecht P. Stroele, Hans-Joachim Wunderlich. 95-101 [doi]
- Pseudo-random testing and signature analysis for mixed-signal circuitsChen-Yang Pan, Kwang-Ting Cheng. 102-107 [doi]
- Efficient and accurate transient simulation in charge-voltage planeAnirudh Devgan. 110-114 [doi]
- A fast wavelet collocation method for high-speed VLSI circuit simulationD. Zhou, N. Chen, W. Cai. 115-122 [doi]
- A formal approach to nonlinear analog circuit verificationLars Hedrich, Erich Barke. 123-127 [doi]
- Constrained multivariable optimization of transmission lines with general topologiesRohini Gupta, Lawrence T. Pileggi. 130-137 [doi]
- Optimal wire sizing and buffer insertion for low power and a generalized delay modelJohn Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin. 138-143 [doi]
- A sequential quadratic programming approach to concurrent gate and wire sizingNoel Menezes, Ross Baldick, Lawrence T. Pileggi. 144-151 [doi]
- High-density reachability analysisKavita Ravi, Fabio Somenzi. 154-158 [doi]
- Hybrid decision diagramsEdmund M. Clarke, Masahiro Fujita, Xudong Zhao. 159-163 [doi]
- Synthesizing Petri nets from state-based modelsJordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev. 164-171 [doi]
- Design verification via simulation and automatic test pattern generationHussain Al-Asaad, John P. Hayes. 174-180 [doi]
- On adaptive diagnostic test generationYiming Gong, Sreejit Chakravarty. 181-184 [doi]
- Diagnosis of realistic bridging faults with single stuck-at informationBrian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee. 185-192 [doi]
- SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuitsNishath K. Verghese, David J. Allstot. 194-198 [doi]
- Extraction of circuit models for substrate cross-talkT. Smedes, N. P. van der Meijs, Arjan J. van Genderen. 199-206 [doi]
- Stable and efficient reduction of substrate model networks using congruence transformsKevin J. Kerns, Ivan L. Wemple, Andrew T. Yang. 207-214 [doi]
- New algorithms for min-cut replication in partitioned circuitsHannah Honghua Yang, D. F. Wong. 216-222 [doi]
- Linear decomposition algorithm for VLSI design applicationsJianmin Li, John Lillis, Chung-Kuan Cheng. 223-228 [doi]
- A gradient method on the initial partition of Fiduccia-Mattheyses algorithmLung-Tien Liu, Ming-Ter Kuo, Shih-Chen Huang, Chung-Kuan Cheng. 229-234 [doi]
- Binary decision diagrams and beyond: enabling technologies for formal verificationRandal E. Bryant. 236-243 [doi]
- Coping with RC(L) interconnect design headachesLawrence T. Pileggi. 246-253 [doi]
- Efficient orthonormality testing for synthesis with pass-transistor selectorsMichel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken. 256-263 [doi]
- Logic decomposition during technology mappingEric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness. 264-271 [doi]
- Efficient use of large don t cares in high-level and logic synthesisReinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash. 272-278 [doi]
- Interface co-synthesis techniques for embedded systemsPai H. Chou, Ross B. Ortega, Gaetano Borriello. 280-287 [doi]
- Communication synthesis for distributed embedded systemsTi-Yen Yen, Wayne Wolf. 288-294 [doi]
- Design-for-debugging of application specific designsMiodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi. 295-301 [doi]
- A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitizationManfred Henftling, Hannes C. Wittmann, Kurt Antreich. 304-309 [doi]
- Acceleration techniques for dynamic vector compactionAnand Raghunathan, Srimat T. Chakradhar. 310-317 [doi]
- LOT: logic optimization with testability-new transformations using recursive learningMitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz. 318-325 [doi]
- An empirical model for accurate estimation of routing delay in FPGAsTanay Karnik, Sung-Mo Kang. 328-331 [doi]
- Performance-driven simultaneous place and route for island-style FPGAsSudip K. Nag, Rob A. Rutenbar. 332-338 [doi]
- Board-level multi-terminal net routing for FPGA-based logic emulationWai-Kei Mak, D. F. Wong. 339-344 [doi]
- Technology mapping for field-programmable gate arrays using integer programmingAmit Chowdhary, John P. Hayes. 346-352 [doi]
- Logic synthesis for look-up table based FPGAs using functional decomposition and support minimizationHiroshi Sawada, Takayuki Suyama, Akira Nagoya. 353-358 [doi]
- Compatible class encoding in Roth-Karp decomposition for two-output LUT architectureJuinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen. 359-363 [doi]
- Estimation of maximum transition counts at internal nodes in CMOS VLSI circuitsChin-Chi Teng, Anthony M. Hill, Sung-Mo Kang. 366-370 [doi]
- Hierarchical timing analysis using conditional delaysHakan Yalcin, John P. Hayes. 371-377 [doi]
- Performance estimation of embedded software with instruction cache modelingYau-Tsun Steven Li, Sharad Malik, Andrew Wolfe. 380-387 [doi]
- Memory bank and register allocation in software synthesis for ASIPsAshok Sudarsanam, Sharad Malik. 388-392 [doi]
- Instruction selection using binate covering for code size optimizationStan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang. 393-399 [doi]
- Fast discrete function evaluation using decision diagramsPatrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia. 402-407 [doi]
- Fast functional simulation using branching programsPranav Ashar, Sharad Malik. 408-412 [doi]
- Gate-level simulation of digital circuits using multi-valued Boolean algebrasScott Woods, Giorgio Casinovi. 413-419 [doi]
- An iterative gate sizing approach with accurate delay evaluationGuangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru. 422-427 [doi]
- Boolean techniques for low power driven re-synthesisR. Iris Bahar, Fabio Somenzi. 428-432 [doi]
- Two-level logic minimization for low powerSasan Iman, Massoud Pedram. 433-438 [doi]
- PARAS: system-level concurrent partitioning and schedulingWing-hang Wong, Rajiv Jain. 440-445 [doi]
- Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniquesMiodrag Potkonjak, Wayne Wolf. 446-451 [doi]
- System partitioning to maximize sleep timeAmir H. Farrahi, Majid Sarrafzadeh. 452-455 [doi]
- A delay model for logic synthesis of continuously-sized networksJoel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinatori Watanabe. 458-462 [doi]
- Power vs. delay in gate sizing: conflicting objectives?Sachin S. Sapatnekar, Weitong Chuang. 463-466 [doi]
- Speeding up pipelined circuits through a combination of gate sizing and clock skew optimizationHarsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn. 467-470 [doi]
- Rectangle-packing-based module placementHiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani. 472-479 [doi]
- An optimal algorithm for area minimization of slicing floorplansWeiping Shi. 480-484 [doi]
- Re-engineering of timing constrained placements for regular architecturesAnmol Mathur, K.-C. Chen, C. L. Liu. 485-490 [doi]
- Power estimation techniques for integrated circuitsFarid N. Najm. 492-499 [doi]
- CAD challenges in multimedia computingPaul E. R. Lippens, Vijay Nagasamy, Wayne Wolf. 502-508 [doi]
- Address generation for memories containing multiple arraysHerman Schmit, Donald E. Thomas. 510-514 [doi]
- Background memory management for dynamic data structure intensive processing systemsGjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wuytack, Francky Catthoor. 515-520 [doi]
- Architectural partitioning of control memory for application specific programmable processorsWei Zhao, Christos A. Papachristou. 521-526 [doi]
- Cost-free scan: a low-overhead scan path design methodologyChih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen. 528-533 [doi]
- A controller-based design-for-testability technique for controller-data path circuitsSujit Dey, Vijay Gangaram, Miodrag Potkonjak. 534-540 [doi]
- On testable multipliers for fixed-width data path architecturesNilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. 541-547 [doi]
- A high-level design and optimization tool for analog RF receiver front-endsJan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen. 550-553 [doi]
- A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital convertersS. R. Kadivar, Doris Schmitt-Landsiedel, H. Klar. 554-561 [doi]
- Statistical behavioral modeling and characterization of A/D convertersEduardo J. Peralías, Adoración Rueda, José Luis Huertas. 562-566 [doi]
- Optimal wiresizing for interconnects with multiple sourcesJason Cong, Lei He. 568-574 [doi]
- Post routing performance optimization via multi-link insertion and non-uniform wiresizingTianxiong Xue, Ernest S. Kuh. 575-580 [doi]
- Single-layer fanout routing and routability analysis for Ball Grid ArraysMan-Fai Yu, Wayne Wei-Ming Dai. 581-586 [doi]
- Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applicationsNelson L. Passos, Edwin Hsing-Mean Sha. 588-591 [doi]
- Time-Constrained Loop PipeliningFermín Sánchez. 592 [doi]
- An iterative improvement algorithm for low power data path synthesisAnand Raghunathan, Niraj K. Jha. 597-602 [doi]
- Symbolic hazard-free minimization and encoding of asynchronous finite state machinesRobert M. Fuhrer, Bill Lin, Steven M. Nowick. 604-611 [doi]
- Sequential synthesis using S1SAdnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 612-617 [doi]
- Design based analog testing by Characteristic Observation InferenceWalter M. Lindermeir, Helmut E. Graeb, Kurt Antreich. 620-626 [doi]
- Dynamic test signal design for analog ICsGiri Devarayanadurg, Mani Soma. 627-630 [doi]
- Impulse response fault model and fault extraction for functional level analog circuit diagnosisChauchin Su, Shenshung Chiang, Shyh-Jye Jou. 631-636 [doi]
- Delay optimal partitioning targeting low power VLSI circuitsHirendu Vaishnav, Massoud Pedram. 638-643 [doi]
- PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlistsRoman Kuznar, Franc Brglez. 644-649 [doi]
- Circuit partitioning with logic perturbationDavid Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska. 650-655 [doi]
- Phantom redundancy: a high-level synthesis approach for manufacturabilityBalakrishnan Iyer, Ramesh Karri, Israel Koren. 658-661 [doi]
- APPlaUSE: Area and performance optimization in a unified placement and synthesis environmentElof Frank, Thomas Lengauer. 662-667 [doi]
- Synthesis of multiplier-less FIR filters with minimum number of additionsMahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh. 668-671 [doi]
- A multiple-dominance switch-level model for simulation of short faultsPeter Dahlgren. 674-680 [doi]
- Fault emulation: a new approach to fault gradingKwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai. 681-686 [doi]
- Functional test generation for delay faults in combinational circuitsIrith Pomeranz, Sudhakar M. Reddy. 687-694 [doi]
- A novel methodology for statistical parameter extractionKannan Krishna, Stephen W. Director. 696-699 [doi]
- Relaxation-based harmonic balance technique for semiconductor device simulationBoris Troyanovsky, Zhiping Yu, Lydia So, Robert W. Dutton. 700-703 [doi]
- Partitioning and reduction of RC interconnect networks based on scattering parameter macromodelsHaifang Liao, Wayne Wei-Ming Dai. 704-709 [doi]
- A unified approach to topology generation and area optimization of general floorplansParthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya. 712-715 [doi]
- A timing-driven data path layout synthesis with integer programmingJaewon Kim, Sung-Mo Kang. 716-719 [doi]
- Signal integrity optimization on the pad assignment for high-speed VLSI designKai-Yuan Chao, D. F. Wong. 720-725 [doi]
- Multi-level logic optimization of FSM networksHuey-Yih Wang, Robert K. Brayton. 728-735 [doi]
- Timing analysis with known false sub graphsKrishna P. Belkhale, Alexander J. Suess. 736-740 [doi]