Table of Contents

• Modeling and synthesis of behavior, control and dataflow (tutorial)Raul Camposano, Andrew Seawright, Joseph Buck. [doi]
• Critical technologies and methodologies for systems-on-chips (tutorial)Wayne Wei-Ming Dai, Howard L. Kalter, Rob Roy, Wayne Wolf. [doi]
• Design technology for building wireless systems (tutorial)Rajesh K. Gupta, Mani B. Srivastava. [doi]
• Timing analysis and optimization: from devices to systems (tutorial)Anirudh Devgan, Leon Stok, Sandip Kundu. [doi]
• PHDD: an efficient graph representation for floating point circuit verificationYirng-An Chen, Randal E. Bryant. 2-7 [doi]
• Functional simulation using binary decision diagramsChristoph Scholl, Rolf Drechsler, Bernd Becker. 8-12 [doi]
• Generalized matching from theory to applicationPatrick Vuillod, Luca Benini, Giovanni De Micheli. 13-20 [doi]
• Decomposition of timed decision tables and its use in presynthesis optimizationsJian Li, Rajesh K. Gupta. 22-27 [doi]
• Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systemsKyosun Kim, Ramesh Karri, Miodrag Potkonjak. 33-38 [doi]
• Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputsZhanping Chen, Kaushik Roy, Tan-Li Chou. 40-44 [doi]
• COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuitsChuan-Yu Wang, Kaushik Roy. 52-55 [doi]
• PRIMA: passive reduced-order interconnect macromodeling algorithmAltan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi. 58-65 [doi]
• A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networksIbrahim M. Elfadel, David D. Ling. 66-71 [doi]
• Multipoint Padé approximation using a rational block Lanczos algorithmTuyen V. Nguyen, Jing Li. 72-75 [doi]
• The disjunctive decomposition of logic functionsValeria Bertacco, Maurizio Damiani. 78-82 [doi]
• Speeding up technology-independent timing optimization by network partitioningRajat Aggarwal, Rajeev Murgai, Masahiro Fujita. 83-90 [doi]
• Negative thinking by incremental problem solving: application to unate coveringEvguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 91-98 [doi]
• Application-driven synthesis of core-based systemsDarko Kirovski, Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith. 104-107 [doi]
• Power optimization using divide-and-conquer techniques for minimization of the number of operationsInki Hong, Miodrag Potkonjak, Ramesh Karri. 108-111 [doi]
• High-level area and power estimation for VLSI circuitsMahadevamurty Nemani, Farid N. Najm. 114-119 [doi]
• Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systemsNaushik Sankarayya, Kaushik Roy, Debashis Bhattacharya. 120-125 [doi]
• Circuit noise evaluation by Padé approximation based model-reduction techniquesPeter Feldmann, Roland W. Freund. 132-138 [doi]
• Global harmony: coupled noise analysis for full-chip RC interconnect networksKenneth L. Shepard, Vinod Narayanan, Peter C. Elmendorf, Gutuan Zheng. 139-146 [doi]
• Efficient coupled noise estimation for on-chip interconnectsAnirudh Devgan. 147-151 [doi]
• Verifying correct pipeline implementation for microprocessorsJeremy R. Levitt, Kunle Olukotun. 162-169 [doi]
• A quantitative approach to functional debuggingDarko Kirovski, Miodrag Potkonjak. 170-173 [doi]
• Approximate timing analysis of combinational circuits under the XBD0 modelYuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton. 176-181 [doi]
• Timing analysis based on primitive path delay fault identificationMukund Sivaraman, Andrzej J. Strojwas. 182-189 [doi]
• Approximate algorithms for time separation of eventsSupratik Chakraborty, David L. Dill. 190-194 [doi]
• Optimization techniques for high-performance digital circuitsChandramouli Visweswariah. 198-205 [doi]
• Sequential optimisation without state space explorationAmit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli. 208-215 [doi]
• Decomposition and technology mapping of speed-independent circuits using Boolean relationsJordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev. 220-227 [doi]
• Scheduling and binding bounds for RT-level symbolic executionChuck Monahan, Forrest Brewer. 230-235 [doi]
• High-level scheduling model and control synthesis for a broad range of design applicationsChih-Tung Chen, Kayhan Küçükçakar. 236-243 [doi]
• Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptionsGanesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha. 244-250 [doi]
• Optimal wire and transistor sizing for circuits with non-tree topologyLieven Vandenberghe, Stephen P. Boyd, Abbas El Gamal. 252-259 [doi]
• Clock-tree routing realizing a clock-schedule for semi-synchronous circuitsAtsushi Takahashi, Kazunori Inoue, Yoji Kajitani. 260-265 [doi]
• A hierarchical decomposition methodology for multistage clock circuitsGary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar. 266-273 [doi]
• A new high-order absolutely-stable explicit numerical integration algorithm for the time-domain simulation of nonlinear circuitsJ. Richard Griffith, Michel S. Nakhla. 276-280 [doi]
• Circuit optimization via adjoint LagrangiansAndrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah, Chai Wah Wu. 281-288 [doi]
• State transformation in event driven explicit simulationTuyen V. Nguyen, Anirudh Devgan. 289-294 [doi]
• A fast and robust exact algorithm for face embeddingEvguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 296-303 [doi]
• An output encoding problem and a solution techniqueSubhasish Mitra, LaNae J. Avra, Edward J. McCluskey. 304-307 [doi]
• OPTIMIST: state minimization for optimal 2-level logic implementationRobert M. Fuhrer, Steven M. Nowick. 308-315 [doi]
• Resource sharing in hierarchical synthesisOliver Bringmann, Wolfgang Rosenstiel. 318-325 [doi]
• Generalized resource sharingSalil Raje, Reinaldo A. Bergamaschi. 326-332 [doi]
• Exploiting off-chip memory access modes in high-level synthesisPreeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau. 333-340 [doi]
• Replication for logic bipartitioningMorgan Enos, Scott Hauck, Majid Sarrafzadeh. 342-349 [doi]
• Partitioning around roadblocks: tackling constraints with intermediate relaxationsShantanu Dutt, Halim Theny. 350-355 [doi]
• Adaptive methods for netlist partitioningWray L. Buntine, Lixin Su, A. Richard Newton, Andrew Mayer. 356-363 [doi]
• Symbolic analysis of large analog circuits with determinant decision diagramsC.-J. Richard Shi, Xiang-Dong Tan. 366-373 [doi]
• A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opampsFrancky Leyn, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen. 374-381 [doi]
• Test generation for comprehensive testing of linear analog circuits using transient response samplingPramodchandran N. Variyam, Abhijit Chatterjee. 382-385 [doi]
• Reachability analysis using partitioned-ROBDDsAmit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 388-393 [doi]
• Record & play: a structural fixed point iteration for sequential circuit verificationDominik Stoffel, Wolfgang Kunz. 394-399 [doi]
• Forward model checking techniques oriented to buggy designsHiroaki Iwashita, Tsuneo Nakata. 400-404 [doi]
• BIST TPG for faults in system backplanesChen-Huan Chiang, Sandeep K. Gupta. 406-413 [doi]
• A test synthesis technique using redundant register transfersChristos A. Papachristou, Mikhail Baklashov. 414-420 [doi]
• Built-in test generation for synchronous sequential circuitsIrith Pomeranz, Sudhakar M. Reddy. 421-426 [doi]
• Hierarchical partitioning for field-programmable systemsVi Chi Chan, David Lewis. 428-435 [doi]
• Hybrid spectral/iterative partitioningJason Y. Zien, Pak K. Chan, Martine D. F. Schlag. 436-440 [doi]
• Large scale circuit partitioning with loose/stable net removal and signal flow based clusteringJason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu. 441-446 [doi]
• IES3: a fast integral equation solver for efficient 3-dimensional extractionSharad Kapur, David E. Long. 448-455 [doi]
• FastPep: a fast parasitic extraction program for complex three-dimensional geometriesMattan Kamon, Nuno Alexandre Marques, Jacob White. 456-460 [doi]
• Transform domain techniques for efficient extraction of substrate parasiticsRanjit Gharpurey, Srinath Hosur. 461-467 [doi]
• EDA and the networkMark D. Spiller, A. Richard Newton. 470-476 [doi]
• Interconnect design for deep submicron ICsJason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo. 478-485 [doi]
• Accurate power estimation for large sequential circuitsJoseph N. Kozhaya, Farid N. Najm. 488-493 [doi]
• Fast power estimation for deterministic input streamsLuca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi. 494-501 [doi]
• Transformational partitioning for co-design of multiprocessor systemsGilberto Fernandes Marchioro, Jean-Marc Daveau, Ahmed Amine Jerraya. 508-515 [doi]
• Hardware/software partitioning for multi-function systemsAsawaree Kalavade, P. A. Subrahmanyam. 516-521 [doi]
• MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systemsRobert P. Dick, Niraj K. Jha. 522-529 [doi]
• NRG: global and detailed placementMajid Sarrafzadeh, Maogang Wang. 532-537 [doi]
• Simulated quenching: a new placement method for module generationShinji Sato. 538-541 [doi]
• A signature based approach to regularity extractionSrinivasa Rao Arikati, Ravi Varadarajan. 542-545 [doi]
• Fault simulation of interconnect opens in digital CMOS circuitsHaluk Konuk. 548-554 [doi]
• GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environmentTzuhao Chen, Ibrahim N. Hajj. 555-561 [doi]
• A deductive technique for diagnosis of bridging faultsSrikanth Venkataraman, W. Kent Fuchs. 562-567 [doi]
• Low power logic synthesis for XOR based circuitsUnni Narayanan, C. L. Liu. 570-574 [doi]
• An exact gate decomposition algorithm for low-power technology mappingHai Zhou, D. F. Wong. 575-580 [doi]
• Trace driven logic synthesis&mdashapplication to power minimizationLuca P. Carloni, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli. 581-588 [doi]
• Performance analysis of a system of communicating processesSujit Dey, Surendra Bommu. 590-597 [doi]
• Embedded program timing analysis based on path clustering and architecture classificationRolf Ernst, Wei Ye. 598-604 [doi]
• Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time systemVincent John Mooney III, Giovanni De Micheli. 605-612 [doi]
• A new approach to simultaneous buffer insertion and wire sizingChris C. N. Chu, D. F. Wong. 614-621 [doi]
• Optimal shape function for a bi-directional wire under Elmore delay modelYouxin Gao, D. F. Wong. 622-627 [doi]
• Global interconnect sizing and spacing with consideration of coupling capacitanceJason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan. 628-633 [doi]
• Test generation for primitive path delay faults in combinational circuitsRamesh C. Tekumalla, Premachandran R. Menon. 636-641 [doi]
• Fast identification of untestable delay faults using implicationsKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal. 642-647 [doi]
• A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlistsPaul Tafertshofer, Andreas Ganz, Manfred Henftling. 648-655 [doi]
• Library-less synthesis for static CMOS combinational logic circuitsSergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David Blaauw. 658-662 [doi]
• Logic synthesis for large pass transistor circuitsPremal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli. 663-670 [doi]
• An exact solution to simultaneous technology mapping and linear placement problemJinan Lou, Amir H. Salek, Massoud Pedram. 671-675 [doi]
• An efficient statistical analysis methodology and its application to high-density DRAMsSang-Hoon Lee, Chang-hoon Choi, Jeong-Taek Kong, Wong-Seong Lee, Jei-Hwan Yoo. 678-683 [doi]
• Fast field solver-programs for thermal and electrostatic analysis of microsystem elementsVladimir Székely, Márta Rencz. 684-689 [doi]
• Post-route optimization for improved yield using a rubber-band wiring modelJeffrey Z. Su, Wayne Wei-Ming Dai. 700-706 [doi]
• Delay bounded buffered tree construction for timing driven floorplanningMaggie Zhiwei Kang, Wayne Wei-Ming Dai, Tom Dillinger, David P. LaPotin. 707-712 [doi]
• Interconnect layout optimization under higher-order RLC modelJason Cong, Cheng-Kok Koh. 713-720 [doi]
• Test and diagnosis of fault logic blocks in FPGAsSying-Jyan Wang, Tsi-Ming Tsai. 722-727 [doi]
• Partial scan delay fault testing of asynchronous circuitsMichael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin. 728-735 [doi]
• Maximum independent sets on transitive graphs and their applications in testing and CADDimitrios Kagaris, Spyros Tragoudas. 736-740 [doi]
• Verifying hardware in its software contextRobert P. Kurshan, Vladimir Levin, Marius Minea, Doron Peled, Hüsnü Yenigün. 742-749 [doi]
• Simulation methods for RF integrated circuitsKenneth S. Kundert. 752-765 [doi]