Table of Contents

• Marsh: min-area retiming with setup and hold constraintsVijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi. 2-6 [doi]
• OPTIMISTA: state minimization of asynchronous FSMs for optimum output logicRobert M. Fuhrer, Steven M. Nowick. 7-13 [doi]
• Bit-level arithmetic optimization for carry-save additionsKei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.. 14-19 [doi]
• Attractor-repeller approach for global placementHussein Etawil, Shawki Areibi, Anthony Vannelli. 20-24 [doi]
• Cell replication and redundancy elimination during placement for cycle time optimizationIngmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz. 25-30 [doi]
• Concurrent logic restructuring and placement for timing closureJinan Lou, Wei Chen, Massoud Pedram. 31-36 [doi]
• Implicit enumeration of strongly connected componentsAiguo Xie, Peter A. Beerel. 37-40 [doi]
• Least fixpoint approximations for reachability analysisIn-Ho Moon, James H. Kukula, Thomas R. Shiple, Fabio Somenzi. 41-44 [doi]
• Lazy group sifting for efficient symbolic state traversal of FSMsHiroyuki Higuchi, Fabio Somenzi. 45-49 [doi]
• Efficient manipulation algorithms for linearly transformed BDDsWolfgang Günther, Rolf Drechsler. 50-54 [doi]
• Noise analysis of non-autonomous radio frequency circuitsAmit Mehrotra, Alberto L. Sangiovanni-Vincentelli. 55-60 [doi]
• New methods for speeding up computation of Newton updates in harmonic balanceMark M. Gourary, Sergey L. Ulyanov, Michael M. Zharov, Sergey G. Rusakov. 61-64 [doi]
• Design and optimization of LC oscillatorsMaria del Mar Hershenson, Ali Hajimiri, Sunderarajan S. Mohan, Stephen P. Boyd, Thomas H. Lee. 65-69 [doi]
• Modeling and simulation of the interference due to digital switching in mixed-signal ICsAlper Demir, Peter Feldmann. 70-75 [doi]
• Provably good algorithm for low power consumption with dual supply voltagesChunhong Chen, Majid Sarrafzadeh. 76-79 [doi]
• A novel design methodology for high performance and low power digital filtersKhurram Muhammad, Kaushik Roy. 80-83 [doi]
• A bipartition-codec architecture to reduce power in pipelined circuitsShanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang. 84-90 [doi]
• AKORD: transistor level and mixed transistor/gate level placement tool for digital data pathsTatjana Serdar, Carl Sechen. 91-97 [doi]
• Analytical approach to custom datapath designSerkan Askar, Maciej J. Ciesielski. 98-101 [doi]
• An integrated algorithm for combined placement and libraryless technology mappingYanbin Jiang, Sachin S. Sapatnekar. 102-106 [doi]
• Timing-driven partitioning for two-phase domino and mixed static/domino implementationsMin Zhao, Sachin S. Sapatnekar. 107-110 [doi]
• Implication graph based domino logic synthesisKi-Wook Kim, C. L. Liu, Sung-Mo Kang. 111-114 [doi]
• Synthesis for multiple input wires replacement of a gate for wiring considerationShih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu. 115-119 [doi]
• Transient sensitivity computation for transistor level analysis and tuningTuyen V. Nguyen, Peter O Brien, David W. Winston. 120-123 [doi]
• An efficient method for hot-spot identification in ULSI circuitsYi-Kan Cheng, Sung-Mo Kang. 124-127 [doi]
• A scalable substrate noise coupling model for mixed-signal ICsAnil Samavedam, Kartikeya Mayaram, Terri S. Fiez. 128-131 [doi]
• Towards true crosstalk noise analysisPinhong Chen, Kurt Keutzer. 132-138 [doi]
• SAT based ATPG using fast justification and propagation in the implication graphPaul Tafertshofer, Andreas Ganz. 139-146 [doi]
• Techniques for improving the efficiency of sequential circuit test generationXijiang Lin, Irith Pomeranz, Sudhakar M. Reddy. 147-151 [doi]
• Concurrent D-algorithm on reconfigurable hardwareFatih Kocan, Daniel G. Saab. 152-156 [doi]
• A new heuristic for rectilinear Steiner treesIon I. Mandoiu, Vijay V. Vazirani, Joseph L. Ganley. 157-162 [doi]
• An implicit connection graph maze routing algorithm for ECO routingJason Cong, Jie Fang, Kei-Yong Khoo. 163-167 [doi]
• The associative-skew clock routing problemYu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelikovsky. 168-172 [doi]
• Efficient incremental rerouting for fault reconfiguration in field programmable gate arraysShantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger. 173-177 [doi]
• Optimal P/N width ratio selection for standard cell librariesDavid S. Kung, Ruchir Puri. 178-184 [doi]
• Performance optimization under rise and fall parametersRajeev Murgai. 185-190 [doi]
• Performance optimization using separator setsYutaka Tamiya. 191-194 [doi]
• Factoring logic functions using graph partitioningMartin Charles Golumbic, Aviad Mintz. 195-199 [doi]
• TICER: realizable reduction of extracted RC circuitsBernard N. Sheehan. 200-203 [doi]
• Realizable reduction for RC interconnect circuitsAnirudh Devgan, Peter R. O Brien. 204-207 [doi]
• RLC interconnect delay estimation via moments of amplitude and phase responseXiaodong Yang, Walter H. Ku, Chung-Kuan Cheng. 208-213 [doi]
• Practical considerations for passive reduction of RLC circuitsAltan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi. 214-220 [doi]
• Formal verification meets simulation (tutorial abstract)Ellen Sentovich, David L. Dill, Serdar Tasiran. 221 [doi]
• Interconnect parasitic extraction in the digital IC design methodologyMattan Kamon, Steve McCormick, Ken Sheperd. 223-231 [doi]
• Cycle time and slack optimization for VLSI-chipsChristoph Albrecht, Bernhard Korte, Jürgen Schietke, Jens Vygen. 232-238 [doi]
• Clock skew scheduling for improved reliability via quadratic programmingIvan S. Kourtev, Eby G. Friedman. 239-243 [doi]
• Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulationChandramouli Visweswariah, Andrew R. Conn. 244-252 [doi]
• Function inlining under code size constraints for embedded processorsRainer Leupers, Peter Marwedel. 253-256 [doi]
• Function unit specialization through code analysisDaniel Benyamin, William H. Mangione-Smith. 257-260 [doi]
• Lower bound on latency for VLIW ASIP datapathsMargarida F. Jacome, Gustavo de Veciana. 261-269 [doi]
• Interface and cache power exploration for core-based embedded system designTony Givargis, Jörg Henkel, Frank Vahid. 270-273 [doi]
• Dynamic power management using adaptive learning treeEui-Young Chung, Luca Benini, Giovanni De Micheli. 274-279 [doi]
• Analytical macromodeling for high-level power estimationGiuseppe Bernacchia, Marios C. Papaefthymiou. 280-283 [doi]
• Parameterized RTL power models for combinational soft macrosAlessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino. 284-288 [doi]
• Validation and test generation for oscillatory noise in VLSI interconnectsArani Sinha, Sandeep K. Gupta, Melvin A. Breuer. 289-296 [doi]
• Fault modeling and simulation for crosstalk in system-on-chip interconnectsMichael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao. 297-303 [doi]
• Robust optimization based backtrace method for analog circuitsAlfred V. Gomes, Abhijit Chatterjee. 304-308 [doi]
• A methodology for correct-by-construction latency insensitive designLuca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli. 309-315 [doi]
• What is the cost of delay insensitivity?Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev. 316-323 [doi]
• Synthesis of asynchronous control circuits with automatically generated relative timing assumptionsJordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens. 324-331 [doi]
• Direct synthesis of timed asynchronous circuitsSung Tae Jung, Chris J. Myers. 332-338 [doi]
• Co-synthesis of heterogeneous multiprocessor systems using arbitrated communicationDavid L. Rhodes, Wayne Wolf. 339-342 [doi]
• Power minimization using system-level partitioning of applications with quality of service requirementsGang Qu, Miodrag Potkonjak. 343-346 [doi]
• Worst-case analysis of discrete systemsFelice Balarin. 347-353 [doi]
• Integrated floorplanning and interconnect planningHung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani. 354-357 [doi]
• Buffer block planning for interconnect-driven floorplanningJason Cong, Tianming Kong, David Zhigang Pan. 358-363 [doi]
• A clustering- and probability-based approach for time-multiplexed FPGA partitioningMango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang. 364-369 [doi]
• The Chebyshev expansion based passive model for distributed interconnect networksJanet Meiling Wang, Ernest S. Kuh, Qingjian Yu. 370-375 [doi]
• Model reduction for DC solution of large nonlinear circuitsEmad Gad, Michel S. Nakhla. 376-379 [doi]
• Efficient model reduction of interconnect via approximate system gramiansJing-Rebecca Li, Jacob White. 380-384 [doi]
• A framework for testing core-based systems-on-a-chipSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. 385-390 [doi]
• Test scheduling for core-based systemsKrishnendu Chakrabarty. 391-394 [doi]
• Partial BIST insertion to eliminate data correlationQiushuang Zhang, Ian G. Harris. 395-399 [doi]
• A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioningHuiqun Liu, D. F. Wong. 400-405 [doi]
• Throughput optimization of general non-linear computationsInki Hong, Miodrag Potkonjak, Lisa M. Guerra. 406-409 [doi]
• Optimal allocation of carry-save-adders in arithmetic optimizationJunhyung Um, Taewhan Kim, C. L. Liu. 410-413 [doi]
• Regularity extraction via clan-based structural circuit decompositionSoha Hassoun, Carolyn McCreary. 414-419 [doi]
• Repeater insertion in tree structured inductive interconnectYehea I. Ismail, Eby G. Friedman, José Luis Neves. 420-424 [doi]
• Interconnect scaling implications for CADRon Ho, Ken Mai, Hema Kapadia, Mark Horowitz. 425-429 [doi]
• Is wire tapering worthwhile?Charles J. Alpert, Anirudh Devgan, Stephen T. Quay. 430-436 [doi]
• Electromagnetic parasitic extraction via a multipole method with hierarchical refinementMichael W. Beattie, Lawrence T. Pileggi. 437-444 [doi]
• Virtual screening: a step towards a sparse partial inductance matrixA. J. Dammers, N. P. van der Meijs. 445-452 [doi]
• A wide frequency range surface integral formulation for 3-D RLC extractionJunfeng Wang, Johannes Tausch, Jacob K. White. 453-458 [doi]
• SOI technology and tools (abstract)Sani R. Nassif, Tuyen V. Nguyen. 459 [doi]
• System level design and debug of high-performance embedded media systems (tutorial)Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar. 461 [doi]
• An approach for improving the levels of compaction achieved by vector omissionIrith Pomeranz, Sudhakar M. Reddy. 463-466 [doi]
• Deep submicron defect detection with the energy consumption ratioBapiraju Vinnakota. 467-470 [doi]
• Efficient diagnosis of path delay faults in digital logic circuitsPankaj Pant, Abhijit Chatterjee. 471-476 [doi]
• Memory bank customization and assignment in behavioral synthesisPreeti Ranjan Panda. 477-481 [doi]
• Memory binding for performance optimization of control-flow intensive behaviorsKamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha. 482-488 [doi]
• Improved interconnect sharing by identity operation insertionDirk Herrmann, Rolf Ernst. 489-493 [doi]
• Formal specification and verification of a dataflow processor arrayThomas A. Henzinger, Xiaojun Liu, Shaz Qadeer, Sriram K. Rajamani. 494-499 [doi]
• Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronizationDragos Lungeanu, C.-J. Richard Shi. 500-504 [doi]
• Synchronous equivalence for embedded systems: a tool for design explorationHarry Hsieh, Felice Balarin. 505-510 [doi]
• On the global fanout optimization problemRajeev Murgai. 511-515 [doi]
• LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and DelayPeyman Rezvani, Amir H. Ajami, Massoud Pedram, Hamid Savoj. 516-519 [doi]
• Optimum loading dispersion for high-speed tree-type decision circuitryJie-Hong Roland Jiang, Iris Hui-Ru Jiang. 520-525 [doi]
• Symbolic functional and timing verification of transistor-level circuitsClayton B. McDonald, Randal E. Bryant. 526-530 [doi]
• Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysisKenneth L. Shepard, Dae-Jin Kim. 531-538 [doi]
• Functional timing optimizationAlexander Saldanha. 539-543 [doi]
• Timing-safe false path removal for combinational modulesYuji Kukimoto, Robert K. Brayton. 544-550 [doi]
• JMTP: an architecture for exploiting concurrency in embedded Java applications with real-time considerationsRachid Helaihel, Kunle Olukotun. 551-557 [doi]
• FunState - an internal design representation for codesignLothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich. 558-565 [doi]
• Fast performance analysis of bus-based system-on-chip communication architecturesKanishka Lahiri, Anand Raghunathan, Sujit Dey. 566-573 [doi]
• Probabilistic state space searchAndreas Kuehlmann, Kenneth L. McMillan, Robert K. Brayton. 574-579 [doi]
• Improving coverage analysis and test generation for large designsJules P. Bergmann, Mark Horowitz. 580-583 [doi]
• Modeling design constraints and biasing in simulation using BDDsJun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz. 584-590 [doi]
• Copyright protection of designs based on multi source IPsEdoardo Charbon, Ilhami Torunoglu. 591-595 [doi]
• Localized watermarking: methodology and application to operation schedulingDarko Kirovski, Miodrag Potkonjak. 596-599 [doi]
• Copy detection for intellectual property protection of VLSI designsAndrew B. Kahng, Darko Kirovski, Stefanus Mantik, Miodrag Potkonjak, Jennifer L. Wong. 600-605 [doi]
• Path toward future CAD environments for MEMS (tutorial abstract)Jacob White, Gary K. Fedder, Tamal Mukherjee. 606 [doi]
• Design of a set-top box system on a chip (abstract)Nikil D. Dutt, Eric M. Foster. 608 [doi]
• On the rapid prototyping and design of a wireless communication system on a chip (abstract)Nikil D. Dutt, Brian Kelley. 609 [doi]
• Advances in transistor timing, simulation, and optimization (tutorial abstract)Jacob White, Jacob Avidan, Abe Elfadel, D. F. Wong. 611 [doi]
• Embedded Java: techniques and applications (tutorial abstract)Reinaldo A. Bergamaschi, Brian M. Barry, John Duimovich. 613 [doi]