Table of Contents

• Storage assignment during high-level synthesis for configurable architecturesWenrui Gong, Gang Wang, Ryan Kastner. 3-6
• Performance-driven read-after-write dependencies softening in high-level synthesisRafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias, Román Hermida. 7-12
• An exact algorithm for the maximal sharing of partial terms in multiple constant multiplicationsPaulo F. Flores, José C. Monteiro, Eduardo A. C. da Costa. 13-16
• FPGA device and architecture evaluation considering process variationsHo-Yan Wong, Lerong Cheng, Yan Lin, Lei He. 19-24
• Via-configurable routing architectures and fast design mappability estimation for regular fabricsYajun Ran, Malgorzata Marek-Sadowska. 25-32
• SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fillKwok-Shing Leung. 33-38
• Computational geometry based placement migrationTao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan. 41-47
• An efficient and effective detailed placement algorithmMin Pan, Natarajan Viswanathan, Chris C. N. Chu. 48-55
• Post-placement rewiring and rebuffering by exhaustive search for functional symmetriesKai-Hui Chang, Igor L. Markov, Valeria Bertacco. 56-63
• Wirelength optimization by optimal block orientationXin Hao, Forrest Brewer. 64-70
• Parametric test development for RF circuits targeting physical fault locations and using specification-based fault definitionsErkan Acar, Sule Ozev. 73-79
• Response shaper: a novel technique to enhance unknown tolerance for output response compactionMango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng. 80-87
• Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCsAnuja Sehgal, Krishnendu Chakrabarty. 88-93
• A cocktail approach on random access scan toward low power and high efficiency testKrishnendu Chakrabarty, J. E. Chen. 94-99
• A statistical study of the effectiveness of BIST jitter measurement techniquesDavid Bordoley, Hieu Nguyen, Mani Soma. 100-107
• The circuit design of the synergistic processor element of a CELL processorOsamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman. 111-117
• Adaptive designs for power and thermal optimizationRichard McGowen. 118-121
• Digital RF processor (DRP/spl trade/) for cellular phonesRobert B. Staszewski, Khurram Muhammad, Dirk Leipold. 122-129
• A layout dependent full-chip copper electroplating topography modelJianfeng Luo, Qing Su, Charles Chiang, Jamil Kawa. 133-140
• Interval-valued statistical modeling of oxide chemical-mechanical polishingJames D. Ma, Claire Fang Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning. 141-148
• Fast and efficient phase conflict detection and correction in standard-cell layoutsCharles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu. 149-156
• IMF: interconnect-driven multilevel floorplanning for large-scale building-module designsTung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin. 159-164
• Robust mixed-size placement under tight white-space constraintsJason Cong, Michail Romesis, Joseph R. Shinnerl. 165-172
• Intrinsic shortest path length: a new, accurate a priori wirelength estimatorAndrew B. Kahng, Sherief Reda. 173-180
• Synthesis methodology for built-in at-speed testingYinghua Li, Alex Kondratyev, Robert K. Brayton. 183-188
• Clustering for processing rate optimizationChuan Lin, Jia Wang, Hai Zhou. 189-195
• ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizingSanghamitra Roy, Weijen Chen. 196-203
• FinFETs for nanoscale CMOS digital integrated circuitsTsu-Jae King. 207-210
• Physics-based compact modeling for nonclassical CMOSVishal P. Trivedi, Jerry G. Fossum, Leo Mathew, Murshed M. Chowdhury, Weimin Zhang, Glenn O. Workman, Bich-Yen Nguyen. 211-216
• Double-gate SOI devices for low-power and high-performance applicationsKaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici. 217-224
• Thermal simulation techniques for nanoscale transistorsJeremy A. Rowlette, Eric Pop, Sanjiv Sinha, Mathew Panzer, Kenneth E. Goodson. 225-228
• An automated technique for topology and route generation of application specific on-chip interconnection networksKrishnan Srinivasan, Karam S. Chatha, Goran Konjevod. 231-237
• Deadlock-free routing and component placement for irregular mesh-based networks-on-chipMartin K. F. Schafer, Thomas Hollstein, Heiko Zimmer, Manfred Glesner. 238-245
• Application-specific network-on-chip architecture customization via long-range link insertionÜmit Y. Ogras, Radu Marculescu. 246-253
• NoCEE: energy macro-model extraction methodology for network on chip routersJeremy Chan, Sri Parameswaran. 254-259
• Architecture and compilation for data bandwidth improvement in configurable embedded processorsJason Cong, Guoling Han, Zhiru Zhang. 263-270
• Code restructuring for improving cache performance of MPSoCsGuilin Chen, Mahmut T. Kandemir. 271-274
• 2D data locality: definition, abstraction, and applicationMahmut T. Kandemir. 275-278
• Integrating loop and data optimizations for locality within a constraint network based frameworkGuilin Chen, Ozcan Ozturk, Mahmut T. Kandemir, Ibrahim Kolcu. 279-282
• System level verification of digital signal processing applications based on the polynomial abstraction techniqueTarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch. 285-290
• Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebraNamrata Shekhar, Priyank Kalla, Florian Enescu, Sivaram Gopalakrishnan. 291-296
• RTL SAT simplification by Boolean and interval arithmetic reasoningGanapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer. 297-302
• Runtime integrity checking for inter-object connectionsGuilin Chen, Mahmut T. Kandemir. 303-306
• Post-placement voltage island generation under performance requirementHuaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang. 309-316
• Buffer insertion under process variations for delay minimizationLiang Deng, Martin D. F. Wong. 317-321
• Efficient algorithms for buffer insertion in general circuits based on network flowRuiming Chen, Hai Zhou. 322-326
• Trade-off between latch and flop for min-period sequential circuit designs with crosstalkChuan Lin, Hai Zhou. 329-334
• Flip-flop insertion with shifted-phase clocks for FPGA power reductionHyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck Chang. 335-342
• Acyclic modeling of combinational loopsAmit Gupta, Charles Selvidge. 343-347
• Fast algorithms for IR drop analysis in large power gridYu Zhong, Martin D. F. Wong. 351-357
• Incremental partitioning-based vectorless power grid verificationDionysios Kouroussis, Imad A. Ferzli, Farid N. Najm. 358-364
• Static timing analysis considering power supply variationsSanjay Pant, David Blaauw. 365-371
• Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automationAndré DeHon, Konstantin Likharev. 375-382
• Performance analysis of carbon nanotube interconnects for VLSI applicationsNavin Srivastava, Kaustav Banerjee. 383-390
• DiCER: distributed and cost-effective redundancy for variation toleranceDi Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, Rabi N. Mahapatra. 393-397
• Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variabilityYasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara. 398-405
• Noise margin analysis for dynamic logic circuitsSuwen Yang, Mark R. Greenstreet. 406-412
• Efficient analog platform characterization through analog constraint graphsFernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli. 415-421
• Performance-centering optimization for system-level analog design explorationXin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih Chen, Wanju Chiang. 422-429
• Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuitsAnuradha Agarwal, Ranga Vemuri. 430-436
• Battery optimization vs energy optimization: which to choose and when?Ravishankar Rao, Sarma B. K. Vrudhula. 439-445
• Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systemsBren Mochocki, Razvan Racu, Rolf Ernst. 446-449
• Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applicationsJaewon Seo, Taewhan Kim, Nikil D. Dutt. 450-455
• Compiler-directed voltage scaling on communication links for reducing power consumptionFeihui Li, Guilin Chen, Mahmut T. Kandemir. 456-460
• Design automation issues for biofluidic microchipsTamal Mukherjee. 463-470
• Design of DNA origamiPaul W. K. Rothemund. 471-478
• Kauffman networks: analysis and applicationsElena Dubrova, Maxim Teslenko, Andrés Martinelli. 479-484
• Parameterized model order reduction of nonlinear dynamical systemsBradley N. Bond, Luca Daniel. 487-494
• Fast-yet-accurate PVT simulation by combined direct and iterative methodsBo Hu, C.-J. Richard Shi. 495-501
• Robust automated synthesis methodology for integrated spiral inductors with variabilityArthur Nieuwoudt, Yehia Massoud. 502-507
• Statistical technology mapping for parametric yieldAshish Kumar Singh, Murari Mani, Michael Orshansky. 511-518
• Reducing structural bias in technology mappingSatrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam. 519-526
• Improving the efficiency of static timing analysis with false pathsShuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris. 527-531
• Total power-optimal pipelining and parallel processing under process variations in nanometer technologyPeter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge. 535-540
• Serial-link bus: a low-power on-chip bus architectureMaged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De. 541-546
• New decompilation techniques for binary-level co-processor generationGreg Stiff, Frank Vahid. 547-554
• Cellular wave computers and CNN technology - a SoC architecture with xK processors and sensor arraysTamás Roska. 557-564
• Eliminating wire crossings for molecular quantum-dot cellular automata implementationAmitabh Chaudhary, Danny Z. Chen, Kevin Whitton, Michael T. Niemier, Ramprasad Ravichandran. 565-571
• Statistical timing analysis driven post-silicon-tunable clock-tree synthesisJeng-Liang Tsai, Lizheng Zhang. 575-581
• TACO: temperature aware clock-tree optimizationMinsik Cho, Suhail Ahmed, David Z. Pan. 582-587
• Statistical based link insertion for robust clock network designWai-Ching Douglas Lam, J. Jam, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen. 588-591
• Practical techniques to reduce skew and its variations in buffered clock networksGanesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert. 592-596
• An efficient and robust technique for tracking amplitude and frequency envelopes in oscillatorsTing Mei, Jaijeet S. Roychowdhury. 599-603
• Oscillator-AC: restoring rigour to linearized small-signal analysis of oscillatorsTing Mei, Jaijeet S. Roychowdhury. 604-609
• A multi-harmonic probe technique for computing oscillator steady statesKapil D. Boianapally, Ting Mei, Jaijeet S. Roychowdhury. 610-613
• Steady-state analysis of voltage and current controlled oscillatorsAmit Mehrotra, Suihua Lu, David C. Lee, Amit Narayan. 618-623
• Timing-aware power noise reduction in layoutChao-Yang Yeh, Malgorzata Marek-Sadowska. 627-634
• A high efficiency full-chip thermal simulation algorithmYong Zhan, Sachin S. Sapatnekar. 635-638
• Fast thermal simulation for architecture level dynamic thermal managementPu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang. 639-644
• Variational analysis of large power grids by exploring statistical sampling sharing and spatial localityPeng Li. 645-651
• The impact of the nanoscale on computing systemsSeth Copen Goldstein. 655-661
• Computer-aided design for DNA self-assembly: process and applicationsChris Dwyer. 662-667
• A mapping algorithm for defect-tolerance of reconfigurable nano-architecturesMehdi Baradaran Tahoori. 668-672
• FastSies: a fast stochastic integral equation solver for modeling the rough surface effectZhenhai Zhu, Jacob K. White. 675-682
• Efficient statistical capacitance variability modeling with orthogonal principle factor analysisRong Jiang, Wenyin Fu, Janet Meiling Wang, Vince Lin, Charlie Chung-Ping Chen. 683-690
• Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductanceMosin Mondal, Yehia Massoud. 691-696
• Statistical critical path analysis considering correlationsYaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark. 699-704
• Discrete Vt assignment and gate sizing using a self-snapping continuous formulationSaumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov. 705-712
• Formalizing designer s preferences for multiattribute optimization with application to leakage-delay tradeoffsSarvesh Bhardwaj, Sarma B. K. Vrudhula. 713-718
• Projection-based performance modeling for inter/intra-die variationsXin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas. 721-727
• System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS)Janet Meiling Wang, Bharat Srinivas, Dongsheng Ma, Charlie Chung-Ping Chen, Jun Li. 728-735
• Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variationsAmit Agarwal, Kunhyuk Kang, Kaushik Roy. 736-741
• Thermal via planning for 3-D ICsJason Cong, Yan Zhang. 745-752
• A routing algorithm for flip-chip designJia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang, Jyh-Herng Wang. 753-758
• An escape routing framework for dense boards with high-speed design constraintsMuhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger. 759-766
• Optimal routing algorithms for pin clusters in high-density multichip modulesMuhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger. 767-774
• Weighted control schedulingAravind Vijayakumar, Forrest Brewer. 777-783
• Hardware synthesis from guarded atomic actions with performance specificationsDaniel L. Rosenband. 784-791
• Fast timing closure by interconnect criticality driven delay relaxationLove Singhal, Elaheh Bozorgzadeh. 792-797
• Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iterationNgai Wong, Venkataramanan Balakrishnan. 801-805
• Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variationsXin Li, Peng Li, Lawrence T. Pileggi. 806-812
• A more reliable reduction algorithm for behavioral model extractionDmitry Vasilyev, Jacob K. White. 813-820
• An efficient method for terminal reduction of interconnect circuits considering delay variationsPu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He. 821-826
• Statistical timing analysis with two-sided constraintsKhaled R. Heloue, Farid N. Najm. 829-836
• A unified framework for statistical timing analysis with coupling and multiple input switchingDebjit Sinha, Hai Zhou. 837-843
• Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variationsXin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi. 844-851
• Verification of executable pipelined machines with bit-level interfacesPanagiotis Manolios, Sudarshan K. Srinivasan. 855-862
• A complete compositional reasoning framework for the efficient verification of pipelined machinesPanagiotis Manolios, Sudarshan K. Srinivasan. 863-870
• Post-verification debugging of hierarchical designsMoayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler. 871-876
• Efficient LTL compilation for SAT-based model checkingRoy Armoni, Sergey Egorov, Ranan Fraer, Dmitry Korchemny, Moshe Y. Vardi. 877-884
• SAT based solutions for consistency problems in formal property specifications for open systemsSuchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti. 885-888
• Architecture and details of a high quality, large-scale analytical placerAndrew B. Kahng, Sherief Reda, Qinke Wang. 891-898
• Mixed-size placement via line searchKristofer Vorwerk, Andrew A. Kennings. 899-904
• A hybrid linear equation solver and its application in quadratic placementHaifeng Qian, Sachin S. Sapatnekar. 905-909
• Energy-efficient platform designs for real-world wireless sensing applicationsPai H. Chou, Chulsung Park. 913-920
• Power-aware microsensor designBrian Schott, Michael Bajura. 921-924
• System software techniques for low-power operation in wireless sensor networksPrabal Dutta, David E. Culler. 925-932
• Expanding the frequency range of AWE via time shiftingAhmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail. 935-938
• A sliding window scheme for accurate clock mesh analysisHongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai. 939-946
• Accurate delay computation for noisy waveform shapesAmit Jain, David Blaauw, Vladimir Zolotov. 947-953
• Pessimism reduction in crosstalk noise aware STAMurat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh. 954-961
• Embedded tutorial: formal equivalence checking between system-level models and RTLAlfred Koelbl, Yuan Lu, Anmol Mathur. 965-971
• CDMA/FDMA-interconnects for future ULSI communicationsM. Frank Chang. 975-978
• The feasibility of on-chip interconnection using antennasK. O. Kenneth, Kihong Kim, Brian A. Floyd, Jesal L. Mehta, Hyun Yoon, Chih-Ming Hung, Daniel F. Bravo, Timothy O. Dickson, Xiaoling Guo, Ran Li, Narasimhan Trichy, James Caserta, Wayne R. Bomstad II, Jason Branch, Dong-Jun Yang, Jose Bohorquez, Jie Chen, Eunyoung Seok, Li Gao, Aravind Sugavanam, Jau-Jr Lin, S. Yu, C. Cao, M.-H. Hwang, Y.-R. Ding, S.-H. Hwang, H. Wu, N. Zhang, Joe E. Brewer. 979-984
• Global signaling over lossy transmission linesMichael P. Flynn, Joshua Jaeyoung Kang. 985-992
• A cache-defect-aware code placement algorithm for improving the performance of processorsTohru Ishihara, Farzan Fallah. 995-1001
• Improving scratch-pad memory reliability through compiler-guided data block duplicationFeihui Li, Guilin Chen, Mahmut T. Kandemir, Ibrahim Kolcu. 1002-1005
• An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systemsAnkur Agiwal, Montek Singh. 1006-1013
• Memory access optimization of dynamic binary translation for reconfigurable architecturesMontek Singh. 1014-1020
• Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computationKaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester. 1023-1028
• Gate sizing using incremental parameterized statistical timing analysisMatthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov. 1029-1036
• Statistical gate sizing for timing yield optimizationDebjit Sinha, Narendra V. Shenoy, Hai Zhou. 1037-1041
• Simulation-based bug trace minimization with BMC-based refinementKai-Hui Chang, Valeria Bertacco, Igor L. Markov. 1045-1051
• Complementary use of runtime validation and model checkingAli Alphan Bayazit, Sharad Malik. 1052-1059
• Scalable compositional minimization via static analysisFadi A. Zaraket, Jason Baumgartner, Adnan Aziz. 1060-1067
• Transition-by-transition FSM traversal for reachability analysis in bounded model checkingMinh D. Nguyen, Dominik Stoffel, Markus Wedler, Wolfgang Kunz. 1068-1075
• Automatic generalized phase abstraction for formal verificationPer Bjesse, James H. Kukula. 1076-1082